Skewed Clock Phase Selection for Mixed-Signal Noise Isolation
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Solution Overview
Problem
In mixed digital/analog systems, the operations of digital components can adversely affect analog components due to noise generated, particularly from clock signals, making it challenging to minimize interference between the two domains without stopping digital component operations.
Innovation Solution
A clock generation component generates multiple clock signals with varying skews for both digital and analog domains, allowing selection of appropriate clock signals to minimize noise interference, with synchronization and calibration schemes to optimize signal-to-noise ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital components operate continuously to maintain system productivity, then productivity is improved, but noise interference to analog components increases
Solution Approach 1:
The patent divides the clock signal into multiple phase segments (e.g., four phases: 0°, 90°, 180°, 270°) and assigns different phases to different digital components. This segmentation allows each component to operate on a different clock phase, effectively distributing the noise in time and reducing simultaneous noise interference to analog components.
Solution Approach 2:
The patent employs periodic switching between different clock phases for digital components. By periodically rotating through different phases in a round-robin fashion, the system ensures that at any given time, some digital components are active while others are inactive, creating periodic noise patterns that can be more easily filtered and reducing peak noise interference.
2Measurement precision
If clock signals are skewed to minimize noise interference, then signal-to-noise ratio is improved, but clock signal synchronization complexity increases
Solution Approach 1:
The patent combines multiple clock phases into a single clock distribution network. A master clock is divided into multiple phases using phase shifters, and these phased clock signals are distributed to different digital components through a unified network. This merging approach maintains signal integrity while achieving noise reduction through phase diversity.
Solution Approach 2:
The patent introduces phase shifters as intermediary components between the master clock source and the digital components. These phase shifters act as mediators that introduce controlled time delays to create the necessary phase skew, enabling noise reduction without requiring direct manipulation of clock signal timing at each component.
3Object-affected harmful factors
If multiple clock phases are generated and distributed, then noise interference is reduced, but clock generation component complexity increases
Solution Approach 1:
The patent employs dynamic phase shifting where the phase relationships between clock signals can be adjusted based on system requirements. Phase shifters are designed to provide variable delay values, allowing the clock generation component to adapt to different operating conditions and optimize noise reduction performance dynamically.
Solution Approach 2:
The patent changes the temporal parameters of clock signals by introducing controlled phase shifts. By modifying the timing parameter (phase angle) of clock signals distributed to different components, the system achieves noise reduction while keeping the frequency and amplitude parameters constant, thus managing complexity through selective parameter modification.
Data Source
AI summary
In one example, a clock generation component is configured to receive a master clock and generate a plurality of clock signals that are shifted relative to one another for a chip having an analog domain and a digital domain. A first selection component is configured to select a first one of the generated clock signals and drive the digital domain according to the first clock signal. A second selection component is configured to select a second one of the generated clock signals that is shifted relative to the first clock signal currently used to drive the digital domain for driving an analog component of the analog domain.