Skewed Current Mirror LDO for Light-Load Transient Stability

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Solution Overview

Problem

Linear voltage regulators face challenges in maintaining bandwidth and transient performance during light load conditions due to high impedance at the gate node, leading to instability and poor response times.

Innovation Solution

Implementing a skewed current mirror with a voltage offset circuit to generate an offset voltage, reducing impedance at the gate node and maintaining low quiescent current, thereby expanding bandwidth and improving transient performance during light loads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a linear regulator is used for voltage regulation, then the circuit is compact and simple, but the bandwidth and transient performance deteriorate during light load conditions due to high impedance at the gate node

Engineering Contradiction:
Improvecircuit simplicityVSAvoidtransient performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies asymmetry by introducing a skewed current mirror configuration where the first and second current mirrors have different scaling factors. This creates an asymmetric impedance distribution that reduces the overall impedance at the gate node during light load conditions, thereby improving bandwidth and transient performance while maintaining the compact linear regulator structure

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent changes the impedance parameter at the gate node by introducing the skewed current mirror with different scaling factors (first scaling factor for first current mirror, second scaling factor for second current mirror). This parameter modification reduces the high impedance condition that causes poor transient performance, allowing the regulator to maintain stability and fast response times during light loads

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the gate node impedance is reduced to improve bandwidth, then transient performance improves, but quiescent current increases

Engineering Contradiction:
Improvetransient performanceVSAvoidquiescent current
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the current mirror scaling factors load-dependent. The first and second current mirrors dynamically adjust their effective scaling based on the load condition, providing low impedance and high bandwidth during light loads while maintaining higher impedance and lower quiescent current during heavy loads. This dynamic adaptation resolves the trade-off between transient performance and power consumption

Inventive Principle:
Principle #15Dynamics

3Loss of energy

If a switching regulator is used instead of linear regulator, then efficiency improves, but circuit complexity and size increase

Engineering Contradiction:
ImproveefficiencyVSAvoidcircuit complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent uses a current mirror-based approach that copies and scales current signals through the skewed current mirror configuration. This allows the linear regulator to achieve switching-regulator-like transient performance through current copying and scaling, avoiding the need for complex switching components while maintaining efficiency benefits

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20250300617A1Voltage regulator with skewed current mirror
Publication Date: 2025.09.25 QUALCOMM INC
  • US20250300617A1 patent drawing
  • US20250300617A1 patent drawing
  • US20250300617A1 patent drawing

AI summary

Techniques and apparatus for supplying power with offset voltage generation are provided. One example power supply circuit generally includes a first transistor including a source coupled to an input voltage (Vin) node and a drain coupled to an output voltage (Vout) node, a second transistor including a drain coupled to a gate of the first transistor, a third transistor including a drain coupled to the drain of the second transistor and to the gate of the first transistor, where a source of the third transistor is coupled to a reference potential node of the power supply circuit, an amplifier including a first input coupled to a reference voltage (Vref) node and an output coupled to a gate of the third transistor, and a voltage offset circuit coupled between the gate of the first transistor and a gate of the second transistor.