Skewed Mapping for Flexible Cache Replication
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Solution Overview
Problem
Current methods for cache line replication in multi-core chips are inefficient due to static and simplistic mapping, leading to variability in replication costs and poor management of cache failures, which result in timing delays and noise across long distances between cores.
Innovation Solution
A method for flexible replication using skewed mapping, where cores are arranged in irregular shapes or patterns with varying distances between home and replica cores, allowing for dynamic reconfiguration and improved fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If static and simplistic mapping is used for cache line replication, then device complexity is reduced, but replication cost variability increases and fault tolerance deteriorates
Solution Approach 1:
The patent implements dynamic remapping of cores to replica cores based on operational status. When a core fails, the system automatically remaps other operational cores to assume the failed core's responsibilities, enabling flexible adaptation to changing system conditions while maintaining high availability
2Ease of operation
If static mapping is used for cache line replication, then ease of operation is improved, but replication cost variability increases
Solution Approach 1:
The system incorporates feedback mechanisms that monitor core operational status and replication performance. Based on this feedback, the system dynamically adjusts the mapping between cores and replica cores to optimize replication costs and ensure consistent performance across different operational conditions
3Adaptability or versatility
If long distances between cores are traversed for data transfer, then adaptability is improved, but timing delays and noise increase
Solution Approach 1:
The patent creates local replica cores positioned adjacent to or near the home core, enabling data to be accessed from nearby locations rather than traversing long distances across the chip. This local quality approach reduces signal propagation distance, minimizing timing delays and noise while maintaining replication flexibility
Data Source
AI summary
For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core.