Skewed Interconnect Via Structure for Lower Resistance and Pullback Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor integrated circuits (ICs) become smaller and more complex, challenges arise in the interconnection of conductive lines and dielectric materials, which are crucial for IC performance improvement.

Innovation Solution

The formation of a skew-like via opening in the dielectric layer, achieved through a combination of anisotropic and isotropic dry etching processes, creates a conductive via with a greater volume, reducing electrical resistance and addressing via pullback issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional via formation processes are used, then the manufacturing process is simple, but the via volume is small resulting in high electrical resistance and via pullback issues

Engineering Contradiction:
Improveelectrical resistanceVSAvoidetching process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The via formation process is segmented into multiple distinct etching stages: anisotropic etching to create the initial via opening, followed by isotropic etching to expand the via volume, and additional anisotropic etching to achieve the final skew-like shape. This segmentation allows each etching step to serve a specific purpose, collectively achieving both high via volume and controlled geometry

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The etching process employs periodic alternation between anisotropic and isotropic etching modes. This periodic action enables the via to be formed with alternating phases of vertical depth control and lateral volume expansion, creating the characteristic skew-like shape that maximizes volume while maintaining proper alignment

Inventive Principle:
Principle #19Periodic action

2Reliability

If conventional via formation processes are used, then the process steps are fewer, but via pullback occurs during thermal treatments

Engineering Contradiction:
Improvevia fixation stabilityVSAvoidnumber of process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The via opening is preliminarily formed with a skew-like shape that includes lateral recesses before subsequent processing steps. This preliminary geometric configuration provides inherent mechanical interlocking with the dielectric layer, preventing via pullback during thermal treatments and subsequent manufacturing processes

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The via geometry transitions from a simple cylindrical shape to a skew-like shape with curved lateral recesses. This curvature creates a mechanical interlock between the via and surrounding dielectric material, providing resistance against pullback forces during thermal processing

Inventive Principle:
Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The screw-like shape of the conductive via enhances its volume, thereby reducing electrical resistance and improving device performance, while also providing a tighter fixation to the dielectric layer, which addresses via pullback issues during thermal treatments.

Implementation Method 1

etching a recess in the dielectric layer above the first metallization layer; etching a first lateral recess in the dielectric layer at a sidewall of the recess

Methodology Applied
Scientific EffectAnisotropic dry etching: Plasma

Implementation Method 2

after etching the first lateral recess, etching the recess downward to expose the first metallization layer

Methodology Applied
Scientific EffectIsotropic dry etching: Plasma

Data Source

PatentUS20250029870A1Interconnection structure and method for forming the same
Publication Date: 2025.01.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250029870A1 patent drawing
  • US20250029870A1 patent drawing
  • US20250029870A1 patent drawing

AI summary

A method for forming an interconnection structure includes depositing a dielectric layer over a first interconnect layer, wherein the first interconnect layer comprises a first metallization layer; forming a via opening in the dielectric layer, and forming a conductive via in the via opening. Forming the via opening includes: etching a recess in the dielectric layer above the first metallization layer; etching a first lateral recess in the dielectric layer at a sidewall of the recess; and after etching the first lateral recess, etching the recess downward to expose the first metallization layer.