Skimming Gate Transistor with Vertical Trench Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing image sensor cells face challenges in maintaining a constant voltage across photosensitive materials, which affects sensitivity and charge collection efficiency due to variations in photocurrent.
Innovation Solution
Incorporation of a skimming gate transistor with a vertical gate electrode structure featuring capacitive deep trench isolations, allowing for controlled conductivity and electrostatic potential management, ensuring consistent voltage and efficient charge collection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional transfer gate transistor structure is used, then the device complexity is reduced, but the voltage across the photosensitive material varies affecting sensitivity and charge collection efficiency
Solution Approach 1:
The patent introduces a vertical gate electrode structure that extends into the substrate, transitioning from a planar gate configuration to a three-dimensional vertical configuration. This vertical dimension allows the gate to exert electrostatic control over the channel more effectively, maintaining constant voltage across the photosensitive material and improving charge collection efficiency without adding lateral device complexity
Solution Approach 2:
The capacitive deep trench isolations serve as intermediary structures between the vertical gate electrode and the substrate. These trenches, filled with conductive or semiconductive material, mediate the electrostatic interaction by providing capacitive coupling that enhances voltage control while electrically isolating adjacent structures, thus resolving the contradiction between improved reliability and device complexity
2Measurement precision
If the skimming gate transistor with vertical gate structure is implemented, then sensitivity and charge collection efficiency are improved, but the manufacturing complexity increases due to capacitive deep trench isolations
Solution Approach 1:
The capacitive deep trench isolations segment the substrate into isolated regions, allowing independent control and optimization of each transistor's electrostatic environment. This segmentation enables precise voltage control for enhanced sensitivity while the modular trench structure can be fabricated using standard deep trench isolation processes, mitigating manufacturing complexity
Solution Approach 2:
The patent utilizes parameter changes in the trench filling material (conductive or semiconductive options) and trench dimensions to optimize the capacitive coupling effect. By adjusting these parameters, the structure achieves improved sensitivity through better voltage control, while the flexibility in material selection allows integration with existing manufacturing processes
3Loss of time
If vertical gate electrode structure with capacitive deep trench isolations is used, then charge transit time is reduced, but the device structure becomes more complex
Solution Approach 1:
The vertical gate electrode extends into the substrate, creating a strong electrostatic field in the vertical dimension that rapidly modulates the channel conductivity. This vertical field configuration reduces charge transit time by enabling faster charge carrier modulation, while the gate structure itself leverages existing vertical trench fabrication capabilities, minimizing the added structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The skimming gate transistor maintains a constant voltage across the photosensitive material, enhancing sensitivity and reducing charge transit time while maintaining steady voltage, thereby improving the overall charge collection efficiency.
Implementation Method 1
each capacitive deep trench isolation of the first and second capacitive deep trench isolations comprises a trench lined with an insulating liner and filled with a conductive or semiconductive material
Implementation Method 2
the photodiode 12 responds to illumination by generating charges at node 14
Data Source
AI summary
An imaging cell includes a skimming gate transistor coupled between a photosensitive charge node and an intermediate node and a transfer gate transistor coupled between the intermediate node and a sense node. The skimming gate transistor includes a vertical gate electrode structure formed by a first capacitive deep trench isolation extending into a substrate and a second capacitive deep trench isolation extending into the substrate. A channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations. Each capacitive deep trench isolation is formed by a trench that is lined with an insulating liner and filled with a conductive or semiconductive material.