Skip Counter for System Timer Power Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic timers in operating systems consume significant CPU resources due to frequent recalculations of timer settings, leading to inaccuracies and preventing CPU shutdown for power conservation, especially in portable devices.
Innovation Solution
A skip counter and signal gate are introduced between a CPU-independent hardware timer and the operating system, allowing interrupts to be delayed until a specific number of timer signals have passed, and a system tick register keeps track of time independently, enabling CPU shutdown and reducing recalculations to whole system ticks upon wake-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic timers are used to control system timing with fractional tick precision, then timing precision is improved, but CPU resource consumption increases significantly
Solution Approach 1:
The system separates timing functions into two segments: a hardware timer that generates periodic interrupts at fixed intervals, and a software skip counter that counts these interrupts to achieve fractional tick precision. This segmentation allows the hardware to handle the energy-intensive periodic generation while the software performs simple increment operations, reducing overall CPU resource consumption while maintaining precision.
Solution Approach 2:
The skip counter acts as an intermediary between the hardware timer and the system tick counter. It receives periodic interrupts from the hardware timer and translates them into fractional tick increments for the system, enabling precise timing control without requiring the CPU to perform complex fractional mathematics directly.
2Measurement precision
If dynamic timers are recalculated after each interrupt to maintain accuracy, then timing accuracy is improved, but system performance deteriorates due to repeated fractional mathematics
Solution Approach 1:
The skip counter is pre-configured with a target value representing the desired fractional tick precision. Instead of performing complex recalculations after each interrupt, the system simply increments the counter and compares it to the pre-set target, eliminating the need for repeated fractional mathematics while maintaining timing accuracy.
3Reliability
If the CPU remains running to serve dynamic timer routines, then timer functionality is maintained, but power consumption increases preventing sleep mode
Solution Approach 1:
The hardware timer operates autonomously, generating periodic interrupts without requiring CPU intervention. The skip counter similarly operates independently, counting interrupts and triggering system tick updates automatically. This self-service capability allows the CPU to enter sleep mode while timing functions continue to operate reliably.
4Measurement precision
If repeated recalculations of timer settings are performed, then timing precision is maintained, but inaccuracies accumulate over time
Solution Approach 1:
The system uses periodic hardware timer interrupts at fixed intervals rather than continuous recalculations. The skip counter accumulates these periodic interrupts in a controlled manner, and system tick updates occur at predetermined intervals based on counter thresholds. This periodic approach prevents the accumulation of timing inaccuracies that occur with repeated recalculations.
Data Source
AI summary
A skip counter timing device employing a typical hardware system timer, a skip counter with a skip count register, a signal gate and a hardware system tick counter as a single sleep mode enhancing skip counter. In an exemplary embodiment, said skip counter is operatively interconnected to a legacy operating system, with said operating system being configured for said interconnection. Use of said skip counter provides the benefits of: 1) allowing CPU shutdown during device sleep modes while 2) eliminating the need for the CPU to perform fractional mathematical calculations in recalculating accurate timer settings upon factional time-slice timer interrupt firings at CPU restarts and thus 3) avoiding overloading CPU resources at said restarts and 4) eliminating incremental and cumulative inaccuracies associated with recalculating timer settings in dynamic timer-managed systems.