Skip Instruction Predicate Logic Pipelined Processor
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Solution Overview
Problem
Pipelined processors without instruction counters face challenges in efficiently skipping instructions based on predicate conditions, as they lack the necessary control circuitry and often require fetching the next instruction after determining a branch, leading to inefficiencies and increased circuit area.
Innovation Solution
A pipelined run-to-completion processor that includes a skip instruction and a companion load predicate instruction, where the skip instruction can skip multiple instructions based on flag values without changing them, and the load predicate instruction sets predicate bits for conditional execution, allowing for efficient execution and reduced circuit complexity by eliminating the need for an instruction counter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a pipelined processor uses conventional branch instructions with instruction counter, then instruction skipping capability is achieved, but circuit area and complexity increase substantially
Solution Approach 1:
The patent removes the instruction counter and its associated control circuitry from the processor architecture. Instead of using traditional branch instructions that rely on an instruction counter to determine target addresses, the design extracts only the essential predicate evaluation logic and skip count functionality, implementing conditional execution through a simpler mechanism that decouples instruction flow control from sequential addressing.
Solution Approach 2:
Rather than using an instruction counter to forward-reference future instruction addresses (traditional approach), the patent inverts the approach by using a skip count field that backward-references the number of instructions to skip from the current position. The predicate bits control whether the skip count is applied, effectively inverting the control flow mechanism from address-based to count-based.
2Ease of operation
If instruction counter and control circuitry are included for branch instructions, then instruction flow control is achieved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the power-consuming instruction counter and its control logic. The essential instruction flow control functionality is retained through a minimal set of components: predicate bit evaluation, skip count storage, and execution stage disabling, which consume significantly less power than traditional branch control circuitry.
3Productivity
If skip instruction decodes multiple instructions, then execution efficiency improves, but decoding stage complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-decoding multiple instructions through the decode stage before execution, allowing the processor to evaluate predicates and prepare skip counts in advance. Instructions are decoded and staged with their predicate conditions evaluated, so that when execution is needed, the work is already prepared, improving throughput without requiring complex runtime decision logic.
Data Source
AI summary
A pipelined run-to-completion processor executes a conditional skip instruction. If a predicate condition as specified by a predicate code field of the skip instruction is true, then the skip instruction causes execution of a number of instructions following the skip instruction to be “skipped”. The number of instructions to be skipped is specified by a skip count field of the skip instruction. In some examples, the skip instruction includes a “flag don't touch” bit. If this bit is set, then neither the skip instruction nor any of the skipped instructions can change the values of the flags. Both the skip instruction and following instructions to be skipped are decoded one by one in sequence and pass through the processor pipeline, but the execution stage is prevented from carrying out the instruction operation of a following instruction if the predicate condition of the skip instruction was true.