Skip-Level Via Landing With Line Extension for Offset Interconnects
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Solution Overview
Problem
Existing semiconductor technologies face challenges in efficiently connecting spaced apart interconnect wiring levels, particularly when they do not align, leading to resistance issues and design limitations in chip manufacturing.
Innovation Solution
The implementation of a skip-level via structure that electrically connects non-aligned interconnect wiring levels by using an extension region in the lowest wiring level, allowing for improved contact area and resistance characteristics, utilizing conductive metals and diffusion barrier liners within dielectric material layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional via structures are used to connect interconnect wiring levels, then alignment between wiring levels is required, but this limits design flexibility and increases manufacturing complexity when wiring levels need to be connected at offset positions
Solution Approach 1:
The patent introduces an extension region that protrudes laterally from the wiring structure in the first interconnect wiring level. This dimensional extension allows the skip-level via structure to connect to the wiring level at an offset position rather than requiring direct alignment, thereby enabling design flexibility for non-aligned interconnect wiring levels while maintaining manufacturing feasibility through a structured approach
2Reliability
If skip-level via structures connect offset wiring structures without an extension region, then the contact area is limited, but this results in higher resistance characteristics
Solution Approach 1:
The extension region is formed in advance within the wiring structure of the first interconnect wiring level before the skip-level via structure is formed. This preliminary extension creates a larger contact area that is available for the via connection, ensuring low resistance characteristics and reliable electrical connection while providing a precise manufacturing target for via formation
3Reliability
If larger contact area is used to reduce resistance, then the area efficiency is improved, but this requires additional space that may conflict with circuit density requirements
Solution Approach 1:
The extension region is implemented locally at specific wiring structures where skip-level via connections are required, rather than uniformly across the entire chip. This localized approach provides the necessary contact area for low resistance connections only where needed, maintaining area efficiency for the overall chip design while enabling reliable electrical connections at critical offset positions
Data Source
AI summary
A skip-level via structure is provided that electrically connects a third level of interconnect wiring to a first level of interconnect wiring or a fourth level of interconnect wiring to a first level of interconnect wiring. In the first instance, the skip-level via structure enables connection even when the first level of interconnect wiring and the third level of interconnect wiring do not line up. In the second instance, the skip-level via structure enables a low resistance connection of the fourth level of interconnect wiring to the first level of interconnect wiring due to increased contact area.