Skip-Level Vias for Dense IC Metallization and Stable Power Delivery
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Solution Overview
Problem
As integrated circuit devices become smaller, the thickness of metallization structures needed for power delivery and thermal spreading is reduced, leading to worsened performance in power delivery and thermal spreading.
Innovation Solution
The implementation of skip level vias in the metallization structure, which extend through multiple dielectric material layers, allowing for reduced critical dimensions without compromising power delivery and thermal spreading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of metallization structures is reduced to achieve smaller device sizes, then the critical dimension can be reduced, but power delivery and thermal spreading performance worsen
Solution Approach 1:
The patent introduces skip-level vias that extend vertically through multiple dielectric layers, utilizing the vertical dimension to create low-resistance power delivery paths. This allows the horizontal metallization thickness to be reduced while maintaining power delivery performance through the vertical via structures that connect power networks across layers.
Solution Approach 2:
The skip-level vias are nested within the multi-layer metallization structure, with conductive material filling vias that penetrate through dielectric layers to connect power networks. This nested configuration enables compact integration while providing robust power delivery paths that compensate for reduced metallization thickness.
2Length of moving object
If the thickness of metallization structures is reduced to achieve smaller device sizes, then the critical dimension can be reduced, but thermal spreading performance worsens
Solution Approach 1:
The skip-level vias create three-dimensional thermal conduction paths through the multi-layer structure. By extending conductive material vertically through dielectric layers, the patent provides additional thermal spreading pathways that compensate for reduced in-plane thermal conduction in thinner metallization layers.
3Reliability
If skip level vias are implemented to reduce critical dimensions, then power delivery performance is maintained, but device complexity increases
Solution Approach 1:
The skip-level vias serve multiple functions simultaneously: they provide low-resistance power delivery paths, enable thermal spreading, and facilitate vertical interconnect between metallization layers. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in overall device complexity.
4Productivity
If skip level vias are implemented to reduce critical dimensions, then higher density of conductive routes is achieved, but manufacturing complexity increases
Solution Approach 1:
The formation of skip-level vias is merged with existing via formation processes in the fabrication sequence. By integrating the skip-level via creation into standard via holes and filling operations, the patent achieves higher conductive route density without proportionally increasing manufacturing complexity.
Data Source
AI summary
An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.