Skip-vias Bypassing Metallization Levels at Minimum Pitch
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Solution Overview
Problem
As semiconductor device dimensions shrink, forming electrical connections through multiple metallization layers becomes increasingly difficult due to complex layout and scaling issues, requiring a method that retains traditional FET structures while overcoming interconnect challenges.
Innovation Solution
A self-aligned skip-via method is developed, which forms a via through a dielectric and metallization layers with a reduced-sized exclusion zone, eliminating the need for patterning in intervening metallization levels and minimizing wiring loss and shorting risks, by selectively widening the via within the metallization layer to create an exclusion zone.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multiple patterning techniques are used to form vias through multiple metallization layers, then electrical connections can be established, but the process complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent extracts the exclusion zone formation from the traditional multiple patterning process. Instead of using registered mask patterns for each metallization layer, the invention forms a single exclusion zone that spans multiple metallization layers by removing material selectively, eliminating the need for complex masking registration while maintaining electrical isolation reliability
Solution Approach 2:
The patent merges multiple patterning steps into a single exclusion zone formation process. By combining the functions of multiple masks and etching cycles into one integrated process, the invention reduces fabrication complexity while still achieving the necessary electrical connections through multiple metallization layers
2Quantity of substance
If device dimensions are shrunk to increase density, then more devices can be placed on substrate, but forming individual components and interconnects becomes more difficult
Solution Approach 1:
The patent changes the geometric parameters of the exclusion zone, making it smaller than traditional exclusion zones. This reduced-sized exclusion zone allows devices to be placed closer together, increasing device density, while the selective material removal process maintains manufacturing feasibility even at these smaller dimensions
3Area of stationary object
If exclusion zone size is reduced to enable smaller pitches, then wiring density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs a self-aligned process where the exclusion zone is automatically positioned relative to the vias through selective material removal. This self-alignment mechanism eliminates the need for complex masking registration, allowing reduced exclusion zone sizes without proportionally increasing manufacturing precision requirements
Data Source
AI summary
A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.