Skip Via Profile Control via Dual Capping Layer Segmentation
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Solution Overview
Problem
The manufacturing process of skip vias in semiconductor structures faces challenges such as blown-out profiles above upper metallization layers, yield loss due to shorting, poor metal fill in high aspect ratio vias, and inadequate gap fills in minimum insulator spacings, leading to decreased device performance.
Innovation Solution
The method involves forming a partial skip via structure by removing a portion of the capping layer and depositing conductive material, followed by forming a thicker capping layer to align and expose the conductive material, ensuring a fully aligned skip via structure with improved profile control and gap fill.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional skip via etching process is used to open the cap, then the skip via connection is achieved, but the profile becomes blown out and yields are lost due to shorting
Solution Approach 1:
The patent segments the capping layer into two distinct layers: a first capping layer that remains intact to protect underlying structures, and a second capping layer that is selectively removed to form the skip via opening. This segmentation allows the etching process to proceed without blowing out the profile, as the first capping layer provides structural support while the second layer is removed in a controlled manner.
Solution Approach 2:
The patent applies preliminary action by forming the first capping layer before removing the second capping layer. This preliminary protective layer is deposited in advance to prevent the blown-out effect during subsequent etching operations, ensuring both profile integrity and yield protection.
2Reliability
If metal fill is performed on high aspect ratio via, then electrical connection is achieved, but metal fill becomes challenging with conventional PVD approach
Solution Approach 1:
The patent changes the geometric parameters of the via structure by controlling the aspect ratio through the dual capping layer approach. The first capping layer provides a broader opening area that facilitates easier metal fill while maintaining the electrical connection function. This parameter change transforms the high aspect ratio challenge into a more manufacturable structure.
3Area of stationary object
If minimum insulator spacing is maintained, then area efficiency is achieved, but adequate gap fills become difficult
Solution Approach 1:
The patent introduces an additional dimensional element by depositing a third capping layer over the filled partial skip via and second capping layer. This third layer provides an extra dimensional buffer that ensures adequate gap fills in minimum insulator spacing while maintaining area efficiency. The additional layer thickness compensates for the reduced spacing, allowing proper gap formation without increasing the horizontal footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a fully aligned skip via structure with enhanced profile control and gap fill, addressing issues of yield loss and device performance by minimizing insulator spacing and ensuring proper metal fill, thereby improving the manufacturing process.
Implementation Method 1
forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping
Implementation Method 2
depositing conductive material in an opening formed in the second metallization layer
Data Source
AI summary
The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.