Skip Via Structures with Hardmask Blocking
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Solution Overview
Problem
The manufacturing process of skip vias in semiconductor structures often results in surface damage to upper wiring structures due to different etch depths, leading to higher resistivity and decreased device performance, and lacks protection for underlying metal layers, while metallization challenges include varying via filling heights during electroless metallization.
Innovation Solution
A method involving the formation of openings in a hardmask material, blocking select openings with a blocking material to control etching, growing a blocking layer on exposed sidewalls to delay via formation, and using a bottom-up fill process to create skip vias that extend to lower metallization features while protecting regular vias, thereby eliminating the need for additional masking levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If skip via etching process is used to connect lower wiring structures, then area efficiency and capacitance minimization are improved, but surface damage occurs to upper wiring structures due to different etch depths
Solution Approach 1:
The patent segments the via formation process into two distinct groups: regular vias that stop at the upper wiring structure level, and skip vias that continue through to lower levels. This is achieved by using separate etching processes with different etch depths, allowing each via type to be optimized independently without causing damage to upper wiring structures.
Solution Approach 2:
The patent applies preliminary protective actions by forming a protective layer or using selective etching conditions before the skip via etching process. This preliminary preparation prevents the etching plasma from damaging the upper wiring structures while still allowing the skip vias to reach the lower levels, thus eliminating the harmful surface damage effect.
2Reliability
If skip via etching extends to lower metallization features, then electrical connection to lower layers is achieved, but underlying metal layers lack protection
Solution Approach 1:
The patent applies local quality by providing selective protection only where needed. Protective layers or liners are formed specifically at the interfaces where skip vias contact lower metallization features, while regular vias receive different protection schemes. This localized approach ensures underlying metal layers are protected at critical interfaces without adding unnecessary complexity elsewhere.
Solution Approach 2:
The patent introduces intermediary protective layers or barrier materials between the skip via conductive material and the underlying metal layers. These intermediary layers serve as mediators that prevent direct contact and potential damage to the underlying metal layers while still allowing electrical connection, thus resolving the contradiction between connection reliability and protection.
3Manufacturing precision
If multiple masking levels are used to control via formation, then manufacturing precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the control of regular via and skip via formation into a single masking step. By using one masking layer with strategically designed opening patterns, both via types are defined simultaneously, eliminating the need for multiple sequential masking operations. This reduces manufacturing complexity while maintaining the precision needed for different via locations and depths.
Solution Approach 2:
The patent creates a universal masking layer that serves multiple functions: defining both regular via openings and skip via openings, controlling etch depths for both via types, and providing alignment references for subsequent processing steps. This multi-functional masking approach replaces what would traditionally require multiple specialized masking layers, reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for controlled etch times and via profiles, reduces manufacturing costs and time, and prevents surface damage to upper wiring structures, ensuring efficient and reliable electrical connections by eliminating the need for multiple masks and protecting underlying metal layers.
Implementation Method 1
growing a blocking material on the exposed sidewalls of the at least one of the openings of the hardmask material to prevent continued via formation of the first via
Implementation Method 2
Metallization of the via structures, such as Cu metallization of via structures, presents other challenges. For example, during an electroless metallization, the via filling height may be different.
Data Source
AI summary
The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.