Skip-Via Proximity Interconnect Without Chamfers
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Solution Overview
Problem
Current back-end-of-line metallization processes face challenges in efficiently forming vias and skip vias without chamfers on dielectric layers, leading to increased design complexity and line lengths, and require multiple wet chemical removal steps.
Innovation Solution
A method involving the formation of a blocking layer and an overlying layer, with resist openings laterally aligned to conductive lines and metallization layers, allowing for trench formation and filling with a metallization layer to create vias and skip vias without chamfers, reducing design complexity and eliminating one wet chemical removal step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional via formation methods are used, then vias can be formed to connect metallization layers, but the process requires multiple wet chemical removal steps and increased design complexity
Solution Approach 1:
The patent extracts and eliminates the chamfering step from the via formation process. By forming vias without chamfers on the dielectric layer, the process removes an unnecessary intermediate step that traditionally required wet chemical removal, thereby simplifying the overall manufacturing process and reducing the number of process steps required
Solution Approach 2:
The patent applies preliminary action by pre-defining the via locations using self-aligned resist openings that are laterally aligned with the conductive lines and metallization layers. This preliminary alignment eliminates the need for subsequent chamfering steps and wet chemical removal, as the via positions are precisely determined in advance through the self-aligned blocking layer approach
2Manufacturing precision
If traditional via formation with chamfers is used, then vias can be formed, but design conductive line lengths increase and footprint increases
Solution Approach 1:
The patent employs self-service through self-aligned via formation where the resist openings automatically align with the conductive lines and metallization layers without requiring additional alignment steps. The blocking layer self-aligns to the underlying structures, enabling precise via placement that minimizes conductive line lengths and reduces the overall design footprint while maintaining manufacturing precision
3Reliability
If multiple wet chemical removal steps are used, then via formation can be completed, but manufacturing time and process complexity increase
Solution Approach 1:
The patent extracts and eliminates the wet chemical removal steps from the via formation process. By using a self-aligned blocking layer approach that forms vias without chamfers, the method removes the need for multiple wet chemical etching and removal operations, thereby reducing manufacturing cycle time while maintaining via formation reliability through the self-aligned process control
Data Source
AI summary
A method of forming vias and skip vias is provided. The method includes forming a blocking layer on an underlying layer, and forming an overlying layer on the blocking layer. The method further includes opening a hole in the overlying layer that overlaps the blocking layer, and etching past the blocking layer into the underlying layer to form a second hole that is smaller than the hole in the overlying layer.