SLAM Accelerator Architecture for Fast Low-Power Pose Mapping
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Solution Overview
Problem
Existing SLAM technologies require high-performance processors for fast computation, leading to increased power consumption and device size, compromising comfort in wearable devices.
Innovation Solution
An apparatus and method for SLAM that utilizes a specialized SLAM accelerator with a factor graph memory and processor, performing front-end and back-end operations efficiently to estimate a peripheral map and pose with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-performance processor is used to perform SLAM operations rapidly, then computation speed is improved, but power consumption increases
Solution Approach 1:
The processor is divided into a general processor and a dedicated SLAM accelerator. The SLAM accelerator handles specific SLAM computation tasks (front-end operations including feature extraction and tracking, and back-end operations including optimization) separately from general processing tasks. This segmentation allows SLAM operations to be performed efficiently with lower power consumption while the general processor handles other device functions.
2Speed
If a high-performance processor is used to perform SLAM operations rapidly, then computation speed is improved, but device size increases
Solution Approach 1:
The processing system is segmented into a general processor for overall device control and a specialized SLAM accelerator for specific SLAM computations. This segmentation allows the SLAM accelerator to be optimized for specific tasks with smaller, more efficient hardware compared to a full high-performance processor, thereby reducing overall device size while maintaining fast SLAM computation.
Solution Approach 2:
The SLAM accelerator acts as an intermediary component between the general processor and the SLAM algorithms. It receives computation requests from the general processor, executes optimized SLAM operations using specialized hardware (including factor graph memory for efficient data storage and retrieval), and returns results to the general processor. This intermediary architecture enables fast SLAM computation without requiring a full high-performance processor.
3Use of energy by moving object
If power consumption is minimized to maintain device comfort, then wearable comfort is improved, but computation speed decreases
Solution Approach 1:
The SLAM accelerator implements local quality optimization by using factor graph memory with a specific data structure that stores only necessary SLAM data (camera poses, map points, and their relationships) in an optimized format. This localized optimization of data storage and retrieval in the memory structure adjacent to the computation unit enables fast SLAM operations with minimal power consumption, as only relevant data is stored and accessed efficiently.
Data Source
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AI summary
An apparatus for accelerating simultaneous localization and mapping (SLAM) includes a SLAM processor including a front-end processor and a back-end processor. The front-end processor is configured to track a position of a first feature, among features extracted from a first frame, in a second frame subsequent to the first frame, and the back-end processor is configured to obtain a first measurement regarding a map point and a camera pose of the first feature based on the position of the first feature in the second frame tracked by the front-end processor, compute elements affecting an optimization matrix in relation to the first measurement, among elements of a Hessian matrix regarding the map point and the camera pose, and accumulate the computed elements in the optimization matrix used to perform an optimization operation with respect to states of the map point and the camera pose.