Slanted Bit Line Contacts for DRAM Trench Depth Reduction
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Solution Overview
Problem
Conventional DRAM device manufacturing faces challenges in miniaturization due to thick doped regions and high resistance of buried bit lines, making it difficult to deepen trenches and integrate high-density memory cells effectively.
Innovation Solution
A semiconductor device with a pillar array and slanted bit line contacts that intersect between pillars, formed using twisted and parallel grooves in the substrate, allowing for reduced trench depth and improved conductivity by using conductive metal bit lines and implanted ion contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If deep trenches are formed in Si substrate to minimize DRAM chip size, then trench width is reduced, but trench depth must be increased which becomes very difficult to perform
Solution Approach 1:
The invention changes the bit line configuration from a single deep horizontal line to multiple slanted contacts arranged in a column array. Each contact is formed at a different lateral position but connects to the same capacitor pillar, effectively distributing the connection path across multiple dimensions and reducing the required trench depth for each individual contact.
Solution Approach 2:
The bit line function is segmented into multiple slanted bit line contacts arranged in a column array. Instead of forming one deep continuous bit line, the connection is divided into multiple discrete contacts that are shallower and easier to form, while collectively achieving the same electrical connection function.
2Reliability
If doped regions are made thick to ensure conductivity, then bit line resistance is reduced, but trench depth must be increased which is difficult for narrow spaces
Solution Approach 1:
The invention transitions from a single thick doped region in a deep trench to multiple thinner doped regions in shallower trenches, arranged in a column array. Each contact has its own doped region that is easier to form with appropriate depth, while the collective array provides sufficient conductivity.
Solution Approach 2:
The invention changes the geometric parameters of the bit line structure from a single deep thick configuration to multiple shallow thinner configurations. By adjusting the number, spacing, and individual dimensions of the slanted contacts, the overall electrical performance is maintained while individual fabrication parameters become more manageable.
3Ease of manufacture
If buried bit lines are made from dopant material, then manufacturing is simplified, but resistance becomes high which adversely affects miniaturization
Solution Approach 1:
The invention uses a composite structure where slanted bit line contacts are formed with conductive metal materials (such as tungsten or copper) combined with doped semiconductor regions. The metal provides low resistance while the doped region provides the necessary electrical connection to the capacitor pillar, achieving both low resistance and ease of manufacture.
Solution Approach 2:
The invention changes the material parameter of the bit line contacts from pure dopant material to conductive metal materials. This material substitution dramatically reduces resistance while the slanted geometry and column array configuration maintain manufacturing simplicity through standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the miniaturization of DRAM devices by reducing trench depth requirements and lowering bit line resistance, facilitating the integration of high-density memory cells while maintaining effective electrical connections.
Implementation Method 1
ion implanting a N+ dopant (such as P, As, or N type ions) into the base 11
Data Source
AI summary
A semiconductor device includes: a substrate having a base and a pillar array including a plurality of pillars; a plurality of bit lines, each of which is disposed between two adjacent ones of the columns of the pillar array; a plurality of word lines, each of which is connected to a corresponding one of the rows of the pillar array; and a contact array including a plurality of bit line contacts arranged in rows and columns. The bit line contacts of each column of the contact array are embedded in the base and are electrically connected to a respective one of the bit lines. Each bit line contact intersects the respective one of the bit lines and extends between and is electrically connected to two adjacent ones of the pillars.