Slanted Nano-FET Gate Electrodes to Prevent Seam Formation
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the reduction in minimum feature size leads to challenges such as the formation of seams or voids during the gate replacement process in nano-FET manufacturing, which affects the integrity and performance of the devices.
Innovation Solution
The implementation of a gate replacement process where funnel-shaped gate electrodes are formed by widening recesses using impurity implantation and selective etching, avoiding the formation of seams by modifying the etch rate of specific regions of the spacers, allowing for improved filling and reducing internal gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional gate replacement process is used with vertical sidewalls, then manufacturing process is simpler, but seams or voids form during gate electrode filling
Solution Approach 1:
The patent applies asymmetry by transitioning from vertical sidewalls to slanted sidewalls in the gate structure. The sidewalls are configured with a specific angle (e.g., 45 degrees) relative to the substrate, creating an asymmetric funnel shape that prevents seam formation during material deposition while maintaining manufacturing feasibility through controlled etching processes.
Solution Approach 2:
The patent changes the geometric parameters of the gate structure by modifying the sidewall angle from vertical (90 degrees) to slanted (e.g., 45 degrees). This parameter change fundamentally alters the filling process dynamics, enabling complete material deposition without voids or seams while managing the increased process complexity through precise parameter control.
2Productivity
If minimum feature size is reduced for higher integration density, then more components can be integrated, but seam formation and device performance deteriorate
Solution Approach 1:
By implementing slanted sidewalls at specific angles, the patent creates an asymmetric geometry that facilitates complete material filling even at reduced feature sizes. This asymmetric design prevents the formation of seams and voids that typically occur in miniaturized vertical structures, thereby maintaining device reliability while achieving higher integration density.
Solution Approach 2:
The slanted sidewall configuration creates a curved, funnel-like geometry that promotes uniform material flow and complete filling during the gate electrode formation process. This curved geometry, as opposed to sharp vertical angles, eliminates stress concentration points and prevents defect formation in miniaturized devices.
3Manufacturing precision
If funnel-shaped gate electrodes are formed with slanted sidewalls, then seam formation is prevented and filling is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the slanted sidewall geometry before gate electrode deposition. The mandrel structure with pre-configured slanted sidewalls is prepared in advance, ensuring that subsequent material deposition automatically follows the desired funnel shape without requiring complex real-time process control during filling.
Solution Approach 2:
The patent uses a mandrel structure as an intermediary element that defines the slanted sidewall geometry. This mandrel serves as a template or mediator that transfers the desired funnel shape to the final gate electrode structure, simplifying the overall manufacturing process by decoupling the complex geometry formation from the material deposition step.
4Reliability
If slanted sidewalls are implemented, then internal gate resistance is reduced and work function is improved, but etch rate control of spacers becomes more critical
Solution Approach 1:
The patent applies local quality by implementing different etch rates in different regions of the spacer structure. The spacers are configured to have region-dependent etch characteristics, with upper and lower portions exhibiting different etch rates relative to the mandrel, enabling precise control of the slanted sidewall angle and overall gate geometry through localized etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and yield of nano-FETs by preventing seam formation and improving the work function of gate electrodes, thereby addressing the limitations of traditional manufacturing methods.
Implementation Method 1
implanting an impurity in upper regions of the gate spacers for the nano-FETs
Data Source
AI summary
In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.