State Look Ahead Quick Pass Write Algorithm for Memory Programming
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Solution Overview
Problem
Current memory programming techniques often result in unnecessary verify operations and extra program pulses, leading to increased time consumption and the risk of over-programming, especially when performing single-state or multi-state bitscans during the programming process.
Innovation Solution
The implementation of a State Look Ahead Quick Pass Write (SLAQPW) algorithm that identifies faster-programming memory cells and applies a bit line voltage to slow them down, allowing for the skipping of verify pulses and reducing the total number of verify operations by triggering the next state verify within the same program loop based on bitscan counts exceeding a threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification pulses are applied to all memory cells during each program loop, then programming completeness can be ensured, but programming time increases and over-programming risk increases
Solution Approach 1:
The patent applies different verify strategies to different groups of memory cells based on their programming characteristics. Fast-programming cells are identified and placed in a separate group that receives fewer verify pulses, while slow-programming cells continue with the standard verify schedule. This local differentiation resolves the contradiction by ensuring reliability for slow cells while reducing time consumption for fast cells.
Solution Approach 2:
The patent performs a preliminary bitscan operation before the main program loop to identify which memory cells are fast-programming cells. This preliminary classification allows the system to apply optimized verify strategies in subsequent loops, reducing overall programming time while maintaining reliability through targeted verification of cells that need it.
2Device complexity
If the same program verify voltage is applied to all memory cells, then simple control is maintained, but programming speed optimization is limited
Solution Approach 1:
The patent dynamically adjusts the program verify voltage based on the identified programming speed characteristics of different memory cell groups. Fast-programming cells receive a first program verify voltage that allows quicker verification, while slow-programming cells receive a second program verify voltage optimized for their characteristics. This dynamic adaptation improves programming speed while keeping control complexity manageable through systematic voltage selection.
3Stability of the object's composition
If all memory cells are programmed at the same pace, then uniform processing is maintained, but faster cells waste time waiting for slower cells
Solution Approach 1:
The patent segments the memory cell population into at least two groups: fast-programming cells and slow-programming cells. This segmentation allows each group to be processed according to its own timing characteristics, with fast cells completing their programming and verification cycles more quickly while slow cells receive the attention they need. The uniform processing structure is preserved through systematic group management, while overall efficiency improves by eliminating waiting time for fast cells.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages associated with the data states targeted for each of the memory cells being programmed during verify loops of a program-verify operation. The control means slows the memory cells targeted for a selected one of the data states identified as being faster to program than other ones of the memory cells during one of verify loops associated with an earlier one of data states.