Slave Clock Frequency Synchronization Using Link Delay Compensation
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Solution Overview
Problem
Current frequency synchronization methods for network devices, where a slave clock calibrates its frequency relative to a master clock, often result in inaccurate frequency offsets due to neglecting changes in link delays, leading to reduced precision in frequency synchronization.
Innovation Solution
The slave clock determines frequency offsets by calculating the first and second delays based on specific packet exchange times between the master and slave clocks, using formulas such as Delay = t2 - t1 + t4 - t3 and Delay' = t2' - t1' + t4' - t3', and then uses these delays along with phase differences to calculate the frequency offset, thereby accounting for changes in link delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the slave clock determines frequency offset using only phase differences without considering link delay changes, then the calculation process is simple, but the frequency synchronization precision is low
Solution Approach 1:
The patent applies preliminary action by measuring and storing link delay values at different time points before using them in frequency offset calculations. The slave clock proactively obtains delay measurements from the master clock at specific moments (t1, t2, t3, t4) and uses these pre-measured values to compensate for link delay changes in the frequency synchronization calculation, thereby improving precision without adding complex real-time measurement mechanisms.
Solution Approach 2:
The patent implements feedback by using the measured link delay changes to adjust and compensate the frequency offset calculation. The slave clock receives delay feedback from the master clock, compares delay values at different time points, and uses this feedback information to correct the frequency synchronization, creating a closed-loop system that continuously improves accuracy based on actual link conditions.
2Measurement precision
If the slave clock measures link delay changes using multiple packet exchanges, then the frequency offset accuracy is improved, but the synchronization process time increases
Solution Approach 1:
The patent merges the link delay measurement process with the frequency synchronization process by using the same packet exchange sequence for both purposes. The four packets (Sync, Delay_Req, Delay_Resp, and frequency offset calculation packets) serve dual functions: establishing time references for delay measurement and providing phase difference data for frequency offset calculation, thereby achieving improved accuracy without proportionally increasing synchronization time.
Solution Approach 2:
The patent applies periodic action by performing delay measurements and frequency synchronization at regular intervals using periodic packet exchanges. The master clock sends Sync packets periodically, and the slave clock performs Delay_Req and Delay_Resp exchanges at scheduled times, allowing the system to maintain accurate synchronization while using efficient, time-bound measurement cycles rather than continuous monitoring.
Data Source
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AI summary
A frequency synchronization method is provided. The method includes: receiving, by a slave clock, a first pulse signal and a second pulse signal; determining, by the slave clock based on a first phase difference, a second phase difference, a first delay, and a second delay, that a frequency offset of the slave clock relative to the master clock is equal to a first frequency offset, where the first phase difference is a difference between a phase of a third pulse signal generated by the slave clock and a phase of the first pulse signal received by the slave clock, and the second phase difference is a difference between a phase of a fourth pulse signal generated by the slave clock and a phase of the second pulse signal received by the slave clock; and calibrating, by the slave clock, frequency of the slave clock based on the first frequency offset. In addition, a corresponding slave clock is further provided. The foregoing solution helps improve frequency synchronization precision.