Slave Clock Synchronization Using Linear Programming
Solution Overview
Problem
Existing packet networks, such as Ethernet, lack inherent timing and synchronization capabilities, leading to issues like call drops and delays in mobile backhaul networks due to lack of accurate time and frequency synchronization, especially when clock transfers occur end-to-end without network assistance.
Innovation Solution
A slave device uses a two-dimensional linear programming technique to estimate clock offset and skew from two-way timing message exchanges under the IEEE 1588 Precision Time Protocol (PTP), allowing for accurate synchronization of a slave clock to a master clock without requiring knowledge of measurement and process noise statistics, and adjusts a skew-adjusted free-running counter to synchronize the slave clock with the master clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If end-to-end clock transfer is used without network assistance, then device complexity is reduced, but measurement precision deteriorates due to packet delay variations
Solution Approach 1:
The patent introduces Boundary Clocks and Transparent Clocks as intermediary devices within the packet network to assist in time synchronization. These intermediate clocks compensate for packet delay variations and provide timing reference points, thereby maintaining synchronization accuracy without requiring complex end-to-end solutions.
Solution Approach 2:
The patent employs dynamic clock adjustment mechanisms where slave clocks continuously adapt their timing based on received synchronization messages and measured packet delay variations. This dynamic adaptation allows the system to maintain precision despite varying network conditions without requiring overly complex static configurations.
2Reliability
If adaptive timing techniques are used to reconstruct timing signals, then reliability improves in the absence of PRC references, but manufacturing precision worsens due to clock wander propagation
Solution Approach 1:
The patent implements feedback mechanisms where slave clocks monitor their synchronization status and adjust their timing based on measured deviations. The clock recovery mechanism uses feedback from timestamp comparisons to continuously correct for frequency drift and wander, maintaining precision while operating independently of PRC references.
Solution Approach 2:
The patent uses preliminary timestamping of packets at both transmit and receive ends to establish reference points before timing reconstruction is needed. These pre-captured timestamps provide a foundation for accurate clock recovery, reducing the propagation of wander even when PRC references are unavailable.
3Ease of operation
If packet-based clock recovery mechanism is used, then ease of operation improves, but measurement precision deteriorates due to packet delay variation effects
Solution Approach 1:
The patent extracts timing information from within the packet data stream itself by embedding timestamps in protocol messages. This extraction of timing data from the packet flow enables straightforward operation while the patent simultaneously addresses precision issues through additional compensation mechanisms.
Solution Approach 2:
The patent changes the parameters used for clock estimation by incorporating multiple timestamp measurements and using statistical methods to filter out packet delay variation effects. This allows the simple packet-based operation to achieve better precision through parameter transformation and data processing.
Data Source
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AI summary
This invention relates to methods and devices for synchronization using linear programming, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a two- dimensional linear programming technique for estimating clock offset and skew, particularly from two-way exchange of timing messages between a master and a slave device. Some embodiments include a skew and offset adjustable free-running counter for regenerating the master time and frequency at the slave device.