Slave Clock Synchronization Using Pulse Width Analysis
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Solution Overview
Problem
In master-slave communication systems, slave devices face challenges in synchronizing their internal clock signals with embedded master clock signals, especially when multiple slave devices communicate through a shared channel, leading to potential disruption and incorrect frequency locking.
Innovation Solution
The implementation of pulse width analysis allows slave devices to determine the frequency of the embedded master clock signal through statistical analysis of varying pulse widths, enabling synchronization without disrupting communication and reducing the need for iterative feedback loop adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a slave device uses traditional CDR process with PLL or DLL to synchronize with the master clock signal, then synchronization can be achieved, but the device may lock onto an incorrect frequency when content is not encoded
Solution Approach 1:
The patent applies preliminary action by performing pulse width analysis on a subset of received pulses before final synchronization. The slave device analyzes pulse widths of initial pulses to determine the correct master clock frequency, establishing a reliable frequency reference before committing to full synchronization. This prevents false locking by pre-validating the frequency based on encoded content characteristics.
2Productivity
If multiple slave devices communicate through a shared channel using time division multiplexing, then communication capacity is improved, but a joining slave device cannot synchronize without disrupting existing communications
Solution Approach 1:
The patent applies the taking out principle by extracting timing information from specific pulse width characteristics of the received signal. The slave device isolates and analyzes the width of individual pulses to determine the master clock frequency, separating the synchronization function from the data content. This allows the slave to acquire synchronization information without needing to interrupt or disrupt the multiplexed communication stream.
3Measurement precision
If a slave device performs iterative feedback loop adjustments to achieve synchronization, then frequency accuracy can be improved, but power consumption and processor cycles increase
Solution Approach 1:
The patent applies self-service by enabling the slave device to autonomously determine the master clock frequency through pulse width analysis of the received signal. Instead of relying on iterative feedback adjustments that require continuous processing and power, the device extracts frequency information directly from the encoded content's pulse characteristics. This self-service approach achieves accurate frequency locking without sustained feedback loop operation, significantly reducing power consumption and processor utilization.
Data Source
AI summary
Disclosed herein include a system and a method of synchronizing a slave device to a signal from a master device based on pulse width analysis. The pulse width analysis is a process to sample the signal at a sampling frequency of the slave device, determine varying pulse widths of the sampled signal, and determine frequency of an embedded master clock signal of the signal based on statistical analysis of the varying pulse widths. Advantageously, performing pulse width analysis allows synchronization of a slave device with the embedded master clock signal in a time and cost efficient manner. In one aspect, determining a frequency of the embedded master clock signal and adjusting an internal clock of the slave device according to the determined frequency is faster and more cost efficient than iteratively adjusting the internal clock based on feedback loop based circuitries.