Slave Clock Synchronization in Non-Deterministic Networks

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Solution Overview

Problem

Existing methods for synchronizing clocks in non-deterministic networks, such as wireless networks, are inefficient due to variable latency and instability, as they rely on continuous control-loops and can take a long time to achieve synchronization, potentially affecting the stability of other clocks derived from the system clock.

Innovation Solution

A step-based approach is used to synchronize clocks in non-deterministic networks by decoupling the slave clock from other clocks, determining and compensating for drift and offset in a single update, allowing for rapid synchronization without continuous drift compensation or control-loops, using synchronization messages and adaptive compensation to maintain stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous control-loops are used for clock synchronization in non-deterministic networks, then synchronization can be maintained, but synchronization time is extended and stability is compromised

Engineering Contradiction:
Improveclock synchronization stabilityVSAvoidsynchronization time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing drift compensation values in a lookup table before actual synchronization is needed. The drift between master and slave clocks is measured and stored in advance, allowing immediate compensation without continuous control loops, thus reducing synchronization time while maintaining stability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by using a step-based approach that adapts the synchronization process to network conditions. Instead of continuous adjustment, the system dynamically selects from pre-calibrated drift compensation values based on measured offset, enabling fast convergence without the instability of continuous control loops

Inventive Principle:
Principle #15Dynamics

2Loss of time

If hard adjustment of slave system clock is performed, then synchronization is achieved quickly, but stability consequences occur for derived clocks

Engineering Contradiction:
Improvesynchronization timeVSAvoidsystem clock stability
Core Design Contradiction:
Loss of timeVSStability of the object's composition

Solution Approach 1:

The patent applies segmentation by separating the slave system clock into two independent components: a stable reference clock that maintains system timing, and a data clock that is adjusted for synchronization. This allows the data clock to be synchronized quickly without affecting the stability of the reference clock and its derived clocks

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts the synchronization function from the system clock by introducing a separate data clock specifically for data transmission timing. The drift compensation is applied only to the data clock through a dedicated synchronization module, leaving the system clock untouched and stable

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If system clock is used for synchronization, then synchronization can be achieved, but all derived clocks exhibit variable frequency

Engineering Contradiction:
Improveclock synchronizationVSAvoidderived clock frequency
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent segments the clock system into a stable reference clock and a separate data clock. The reference clock continues to provide stable timing for all derived clocks, while the data clock is specifically adjusted for synchronization with the master clock, preventing frequency variability from propagating to derived clocks

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3235156B1Method of synchronising clocks of network devices
Publication Date: 2022.04.06 ROBERT BOSCH GMBH
  • EP3235156B1 patent drawingFigure 1
  • EP3235156B1 patent drawingFigure 2a
  • EP3235156B1 patent drawingFigure 2b

AI summary

The invention relates to a method of synchronising clocks of network devices (100, 200), preferably in a non-deterministic network (1) with a channel access method, wherein it is not possible to determine a time needed for a network device to access the non-deterministic network (1), wherein each network device (100, 200) comprises at least one clock, wherein a first clock of a first network device (100) and a second clock (VCXOa) of a second network device (200) differ by an offset and the offset changes over time due to a drift and wherein the second clock (VCXOa) of a second network device (200) shall be synchronised with the first clock of the first network device (100), wherein the second clock (VCXOa) of the second network device (200) is adapted separately from any other clocks of the second network device (200) and separately from any other clock of any other network device and wherein the drift between the clock of the first network device (100) and the clock (VCXOa) of the second network device (200) is determined and compensated for.