Slave Clock Compensation for Bounded Network Time Offset

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Solution Overview

Problem

Existing clock synchronization methods, such as those using GNSS receivers and packet-based frequency synchronization, are costly and fail to ensure a bounded time offset between master and slave nodes, leading to inaccuracies and jitters in network timing.

Innovation Solution

A clock synchronization method that determines a compensation parameter based on the mapping relationship between a master clock and a slave node's reference timescale, using timestamps to establish a time combination and perform clock synchronization, ensuring a bounded time offset through statistical calculations and frequency locking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If packet-based frequency synchronization is used, then frequency offset between master and slave clocks is maintained within a specific range, but time offset between the clocks is not bounded

Engineering Contradiction:
Improvefrequency synchronization accuracyVSAvoidtime offset boundedness
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent changes the synchronization parameter from frequency-only to time-based by using timestamps and establishing a mapping relationship between master clock and slave node reference timescale. This allows the system to maintain both frequency and time synchronization, bounding the time offset while preserving frequency accuracy.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback by continuously monitoring the mapping relationship between master clock timestamp and slave node reference timescale timestamp, calculating compensation parameters, and adjusting the slave clock accordingly. This closed-loop feedback ensures time offset boundedness while maintaining frequency synchronization.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If GNSS receiver is used for time/phase synchronization, then accurate time synchronization is achieved, but implementation cost becomes very high

Engineering Contradiction:
Improvetime synchronization accuracyVSAvoidhardware cost
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent creates a virtual timing reference by establishing a mapping relationship between master clock and slave node reference timescale through timestamp comparison. This software-based timing reference copies the functionality of expensive GNSS receivers without requiring external satellite hardware, achieving accurate time synchronization through packet-based timestamp analysis.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent replaces the mechanical/GNSS-based time synchronization system with a software-based packet timestamp analysis system. By using timestamp mapping and compensation parameters calculated from network packets, the system substitutes expensive external hardware with software processing, eliminating the need for GNSS receivers while maintaining synchronization accuracy.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Stability of the object's composition

If SyncE is used for frequency synchronization, then stable frequency allocation is provided, but time or phase synchronization cannot be provided

Engineering Contradiction:
Improvefrequency stabilityVSAvoidtime synchronization capability
Core Design Contradiction:
Stability of the object's compositionVSMeasurement precision

Solution Approach 1:

The patent merges frequency synchronization (from SyncE) with time synchronization by combining the stable frequency reference with timestamp-based time reference establishment. The mapping relationship between master clock and slave node reference timescale integrates both frequency and time information, allowing the system to provide both stable frequency allocation and accurate time/phase synchronization simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4665017A1Clock synchronization method and device
Publication Date: 2025.12.17 HUAWEI TECH CO LTD
  • EP4665017A1 patent drawingFigure 1
  • EP4665017A1 patent drawingFigure 2
  • EP4665017A1 patent drawingFigure 3

AI summary

Embodiments of this application provide a clock synchronization method and an apparatus. The clock synchronization method is applied to a slave node. The clock synchronization method includes: receiving a synchronization packet sent by a master node, where the synchronization packet carries a master clock timestamp of the master node; establishing a mapping relationship between a master clock of the master node and a reference timescale of the slave node based on the master clock timestamp and a timestamp corresponding to a reference timescale of the slave node when the slave node receives the synchronization packet; obtaining a time combination of the timestamp corresponding to the reference timescale of the slave node and slave clock time of the slave node, where a collection moment of the reference timescale of the slave node and a collection moment of the slave clock time corresponding to the reference timescale are the same; and determining a compensation parameter based on the mapping relationship and the time combination, to perform clock synchronization between the slave node and the master node based on the compensation parameter. In this application, the slave clock time of the slave node is compensated by using the compensation parameter, to ensure that a time offset between the master node and the slave node is bounded.