Slave Device Address Identification Using Delay Signal Timing
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Solution Overview
Problem
Programmable logic chips like CPLD/FPGA lack analog-to-digital converters, making it difficult to distinguish between slave devices based on voltage levels, and occupying too many pins when forming matrices for identification, leading to resource constraints.
Innovation Solution
Implementing a delay unit in each slave device that outputs a delay signal to the main board, allowing the main board to compute and match delay times with pre-stored address information, thus identifying slave devices without requiring additional I/O pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage level values are used to distinguish slave devices, then identification can be achieved, but CPLD/FPGA cannot perform this function due to lack of analog-to-digital converter
Solution Approach 1:
The patent replaces the voltage-level-based identification method (which requires analog-to-digital conversion) with a time-based delay measurement method. Instead of measuring voltage levels that require analog conversion, the system measures delay times using digital timing capabilities, allowing CPLD/FPGA to identify slave devices without analog-to-digital converter pins.
Solution Approach 2:
The patent changes the identification parameter from voltage level (analog domain) to delay time (temporal domain). By measuring the time delay between clock signals and slave device responses, the system achieves slave device identification using only digital timing resources available in CPLD/FPGA, eliminating the need for analog-to-digital conversion.
2Measurement precision
If matrix formation is used to distinguish slave devices, then identification can be achieved, but the number of pins occupied increases significantly
Solution Approach 1:
The patent extracts the essential identification information from the full matrix of signal combinations and uses only the time delay characteristic. Instead of requiring multiple pins to form and read complete signal matrices, the system extracts delay time information from a single timing measurement, significantly reducing the number of required I/O pins while maintaining identification capability.
Solution Approach 2:
The patent uses a partial measurement approach by measuring only the delay time parameter rather than capturing the complete signal matrix. This partial action (measuring delay time) is sufficient for identification purposes, avoiding the excessive action of requiring full matrix formation and reading that would demand many more pins.
3Adaptability or versatility
If more slave devices are connected to distinguish between them, then identification capability increases, but the I/O pin resource becomes insufficient
Solution Approach 1:
The patent adds the time dimension to the identification process by measuring delay times. This temporal dimension provides additional identification capacity without requiring more spatial pins. By measuring how long it takes for slave devices to respond to clock signals, the system can uniquely identify more devices using the same physical pin count, effectively using time as an additional identification dimension.
Data Source
AI summary
In a method and system for identifying addresses of slave devices, the system includes a main board, slave devices, and a power source. The main board is electrically connected to the slave devices and a delay unit is set in each slave device. An output terminal of the delay unit is electrically connected to the main board. The delay unit outputs a delay signal to the main board when first powered on, the main board receives the delay signal, computes a delay time of the delay signal, and by reference to a preset table identifies the slave device based on the specific delay time. Occupation of input and output I/O pins is reduced, a device for identifying addresses of slave devices is also disclosed.