Slave Device Virtual Address Translation
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Solution Overview
Problem
Existing microprocessor systems face inflexibility when adding or changing slave devices, as they require new hardware drivers due to different interfaces, and address misses in virtual addressing can lead to incomplete access requests without proper resolution mechanisms on slave devices.
Innovation Solution
A slave device with capabilities to identify and store access requests, including write and read operations, allowing it to handle address misses independently without involving the master device, using local memory for storing necessary data and employing address mapping and translation to respond to requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a slave device uses a fixed interface with predetermined address mapping, then the interface is simple and reliable, but the system loses flexibility when adding or changing slave devices
Solution Approach 1:
The slave device autonomously identifies address misses and handles them independently using local memory, without requiring master device intervention. This self-service capability resolves the contradiction by enabling flexible address mapping while maintaining simple communication protocols.
Solution Approach 2:
The slave device pre-loads data into local memory before the master device needs it, based on predicted access patterns. This preliminary action enables the slave to handle address misses independently, providing flexibility without increasing interface complexity.
2Reliability
If the slave device handles address misses independently, then access requests can be completed without master device involvement, but the slave device requires more complex local memory and identification capabilities
Solution Approach 1:
The address space is segmented into regions that map to specific local memory areas in the slave device. This segmentation enables the slave to independently identify and handle address misses by comparing the accessed address against predetermined mappings, ensuring reliable access completion without excessive complexity.
Solution Approach 2:
Local memory in the slave device acts as an intermediary between the communication bus and the slave's internal resources. It stores data that can be quickly retrieved when address misses occur, enabling reliable access handling while keeping the slave device's complexity manageable.
3Adaptability or versatility
If virtual addressing is implemented on the slave device, then memory management flexibility is improved, but address mapping and translation complexity increases
Solution Approach 1:
The slave device implements virtual addressing with local quality by maintaining predetermined mappings specific to its own address space and resources. Each slave device can have its own custom mapping scheme optimized for its particular memory management needs, providing flexibility without requiring complex system-wide translation mechanisms.
Data Source
AI summary
A slave device (20) communicates with a host system (21) via a host communications bus (22). The host system (21) includes one (or more) processing units that can act as bus masters and send access requests for slave resources on the slave device (20) via the communications bus (22). The slave device platform (20) includes a memory management unit (23), a programmable central processing unit (24) and one or more slave resources (25). The memory management unit (23) acts as an address translating device, and accepts requests with virtual addresses from the master device or devices on the host system (21), translates the virtual addresses used in the access requests to the “internal” physical addresses of the slave's resources and forwards the accesses of the appropriate physical resources (25). When an address miss occurs in the memory management unit (23), it passes the handling of the access request over to the controlling CPU (24) which executes software to then resolve the address miss and handle the access request. The memory management unit (23) also includes a write buffer (29) into which it can write the write value received from a master on the host system (21) on an access when an address miss occurs, and a read buffer (28) for storing values relating to read requests that have generated an address miss.