Slave DLL Dummy Load Circuit for Delay Fluctuation Control
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Solution Overview
Problem
Delay lock loop (DLL) systems experience supply voltage deviation and bias voltage deviation due to parasitic capacitance fluctuations when a slave DLL starts or stops operation, leading to delay fluctuations in both master and slave DLLs, which conventional large capacitors insufficiently address, requiring additional power and circuit space.
Innovation Solution
The implementation of a dummy load and dummy slave DLLs, along with variable capacitance selection and current mirror circuitry, helps minimize supply voltage and bias voltage deviations by controlling the enablement of dummy loads and slave clocks, stabilizing the DLL system's timing under varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional large capacitors are used to address supply voltage deviation, then supply voltage stability is improved, but circuit area and power consumption increase
Solution Approach 1:
A dummy load circuit is introduced as an intermediary component to absorb supply voltage deviations and parasitic capacitance fluctuations. The dummy load acts as a mediator between the power supply and the DLL circuit, stabilizing the supply voltage without requiring large capacitors that would increase circuit area.
Solution Approach 2:
The dummy load circuit replicates the electrical characteristics of the actual DLL load. By creating a copy of the load behavior, the dummy load can effectively compensate for voltage fluctuations and parasitic effects without duplicating the entire DLL circuit structure, thus minimizing area overhead.
2Stability of the object's composition
If conventional large capacitors are used to address bias voltage deviation, then bias voltage stability is improved, but circuit area and power consumption increase
Solution Approach 1:
The dummy load circuit serves as an intermediary that stabilizes bias voltage by absorbing parasitic capacitance fluctuations. This approach avoids the need for large compensation capacitors that would consume significant power while achieving the same voltage stability effect.
Solution Approach 2:
The invention changes the operational parameters of the dummy load circuit to match the characteristics of the actual DLL circuit. By adjusting the dummy load's electrical parameters (resistance, capacitance) to mirror the real load, the circuit achieves effective voltage stabilization with minimal power overhead.
3Adaptability or versatility
If slave DLL starts or stops operation, then system adaptability is improved, but delay fluctuation increases due to parasitic capacitance changes
Solution Approach 1:
The dummy load circuit is pre-configured to compensate for parasitic capacitance effects before the slave DLL actually starts or stops operation. This preliminary compensation action prevents delay fluctuations from occurring in the first place, maintaining stability during adaptive state transitions.
Solution Approach 2:
The system employs feedback mechanisms to detect parasitic capacitance changes when the slave DLL transitions between states. The dummy load circuit adjusts its characteristics in real-time based on this feedback, maintaining delay stability while allowing the system to remain adaptable to different operational states.
Data Source
AI summary
A device includes a master delay-lock loop (DLL) having a phase frequency detector connected in series with a charge pump that is to generate a control voltage. A slave DLL is coupled to the master DLL and has a delay line including a buffer to receive a slave clock and a series of delay cells coupled between the buffer and an output terminal that is to output a delay clock, the series of delay cells variably controlled by the control voltage. The master DLL and the slave DLL are powered by a power supply that experiences undershoot or overshoot in response to a load transient. A dummy load is coupled between the delay line of the slave DLL and an output of the power supply, the dummy load including an exclusive OR gate that receives, as inputs, a first output of the buffer and the delay clock.