Slave DLL Offset Calibration for Fast Idle-to-Active Clock Recovery
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Solution Overview
Problem
In DRAM systems, particularly in graphics double data rate (GDDR) systems, the DLL circuits face challenges in maintaining lock during idle periods due to voltage and temperature drifts, leading to increased time and difficulty in re-establishing clock integrity when transitioning from idle to active mode.
Innovation Solution
A clocking circuit comprising a master DLL, a slave DLL, and an arbiter circuit that temporarily enables a replica phase detector during idle periods to update configuration values and adjust delay elements, ensuring accurate clock synchronization by canceling offset between master and slave DLLs through a local replica feedback loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DLL is idled during non-read periods to save power, then power consumption is reduced, but voltage and temperature conditions drift without compensation making re-lock more time-consuming and difficult
Solution Approach 1:
The patent applies preliminary action by performing offset calibration during idle periods before actual read operations begin. The replica phase detector is temporarily enabled during idle time to update configuration values and compensate for drift, so that when the DLL becomes active again, it is already calibrated and ready for immediate operation without requiring extended re-lock time.
Solution Approach 2:
The patent implements periodic action by enabling the replica phase detector at specific intervals during idle periods rather than continuously. The arbiter circuit temporarily activates the replica phase detector based on calibration signals, performing offset calibration periodically during non-read periods while keeping the DLL idled, thus balancing power savings with maintenance of clock integrity.
2Reliability
If the replica phase detector is continuously enabled to maintain calibration, then clock integrity is maintained, but power consumption increases
Solution Approach 1:
The patent uses periodic action by enabling the replica phase detector only during specific idle periods when calibration is needed, rather than continuously. The arbiter circuit controls the temporary activation based on calibration signals, allowing the system to maintain clock integrity through periodic calibration while minimizing power consumption by keeping the replica phase detector disabled during active read operations.
Solution Approach 2:
The patent applies dynamics by making the replica phase detector's operation dynamic rather than static. The arbiter circuit temporarily enables or disables the replica phase detector based on system state and calibration needs, allowing the system to adapt power consumption and calibration activity to actual operational requirements, thus maintaining reliability while optimizing power usage.
3Reliability
If the DLL operates continuously to maintain lock, then clock synchronization is maintained, but power consumption increases and idle period benefits are lost
Solution Approach 1:
The patent applies preliminary action by performing offset calibration during idle periods before the DLL needs to become active again. This preliminary calibration ensures that when the DLL transitions from idle to active mode, it starts with accurate timing relationships already established, maintaining synchronization reliability without requiring continuous operation.
Solution Approach 2:
The patent uses an intermediary approach by introducing a replica phase detector that can operate independently during idle periods to maintain calibration. This replica detector acts as an intermediary that preserves timing information and offset calibration without requiring the main DLL to remain fully operational, thus maintaining synchronization capability while reducing power consumption during idle states.
Data Source
AI summary
A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code. The replica phase detector is then disabled.