Slave-Initiated Interrupts on RFFE Clock Line

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current RFFE bus protocols face latency issues and power consumption challenges due to periodic polling for interrupt conditions, which can lead to non-compliance with stringent cellular protocols and unnecessary power drain.

Innovation Solution

Implementing slave-initiated interrupts on the RFFE bus, where a slave drives the clock line to a non-idle state to indicate an interrupt condition, allowing the master to initiate a polling sequence earlier and reducing unnecessary polling, thereby reducing latency and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If periodic polling is used to detect interrupt conditions on the RFFE bus, then the master can detect slave status, but latency increases and cellular protocol compliance deteriorates

Engineering Contradiction:
Improveinterrupt detection latencyVSAvoidcellular protocol compliance
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

Instead of the master polling the slave to detect interrupt conditions, the slave actively signals the master by driving the clock line to a non-idle state when an interrupt condition occurs. This inversion of the detection initiative reduces latency from 1ms polling intervals to near-real-time notification, ensuring cellular protocol compliance while maintaining reliable interrupt detection.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The slave prepares and signals interrupt conditions immediately when they occur, rather than waiting for the next polling cycle. By driving the clock line to a non-idle state as soon as an interrupt condition is detected, the slave performs preliminary action that triggers immediate master response, eliminating the waiting period inherent in periodic polling and reducing overall latency.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If periodic polling occurs frequently to reduce latency, then interrupt detection improves, but power consumption increases due to unnecessary polling cycles

Engineering Contradiction:
Improveinterrupt detection latencyVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The detection initiative is inverted from master-to-slave polling to slave-to-master signaling. The slave drives the clock line to a non-idle state only when an interrupt condition occurs, eliminating continuous or frequent polling cycles. This approach achieves near-real-time interrupt detection while consuming minimal power, as the bus remains idle until actually needed.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The unnecessary periodic polling cycles are extracted and removed from the system. Only essential interrupt signaling moments activate the bus, with the slave driving the clock line to a non-idle state solely when interrupt conditions occur. This extraction of redundant polling operations eliminates wasted power consumption while maintaining responsive interrupt detection.

Inventive Principle:
Principle #2Taking out (Extraction)

3Stability of the object's composition

If the clock line is held at logical low during idle state, then the bus maintains a defined idle state, but the slave must actively drive it high to signal an interrupt

Engineering Contradiction:
Improvebus idle state stabilityVSAvoidinterrupt signaling mechanism
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The interrupt signaling mechanism inverts the conventional approach by having the slave drive the clock line to a non-idle state (logical high) to signal interrupts, rather than the master polling the slave. The clock line is held at logical low during idle states to maintain stability, and the slave's active driving to logical high provides a clear, unambiguous interrupt signal that is simple to detect and process.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentEP3491786B1Slave initiated interrupts for a communication bus
Publication Date: 2020.05.13 QUALCOMM INC
  • EP3491786B1 patent drawingFigure 1
  • EP3491786B1 patent drawingFigure 2
  • EP3491786B1 patent drawingFigure 3

AI summary

Slave initiated interrupts for a communication bus are disclosed. In one aspect, the communication bus is a radio frequency front end (RFFE) bus, and a slave is allowed to indicate to a master on the RFFE bus that the slave has an interrupt condition. On receipt of a slave initiated interrupt, the master may initiate a polling sequence to determine which of a plurality of slaves associated with the RFFE bus initiated the interrupt and process the interrupt accordingly. Continuing the exemplary aspect, the slave may indicate the interrupt condition to the master by driving a clock line of the RFFE bus to a non-idle state. The master may detect this manipulation of the clock line and initiate the polling sequence.