Retention Flip-Flop Slave Latch Switching for Power-Down Data Hold
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Solution Overview
Problem
In digital circuits and SoCs, power leakage during idle or sleep modes leads to significant power consumption, and temporarily cutting off power to flip-flops to reduce this consumption results in data loss when power is resumed.
Innovation Solution
A retention flip-flop design with a master latch, slave latch, and control logic that allows the slave latch to operate in an open loop during normal operation and form a closed loop during power-down mode, maintaining data by using separate power sources and control signals to manage power states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is continuously supplied to the flip-flop to maintain data storage, then data retention is ensured, but power consumption increases during idle and sleep modes
Solution Approach 1:
The patent applies dynamics by making the power supply state changeable based on operational mode. The flip-flop can dynamically switch between being powered on (during active mode for data storage) and powered off (during idle/sleep modes to reduce leakage), while a separate retention latch maintains data when powered off. This dynamic power state management resolves the contradiction between continuous power supply for data retention and power reduction during low-activity periods.
2Loss of energy
If power is cut off to the flip-flop during idle and sleep modes to reduce power consumption, then power leakage is reduced, but data is lost when power is resumed
Solution Approach 1:
The patent segments the flip-flop into two independent parts: the main flip-flop circuit (master latch and slave latch) that can be powered off to reduce leakage, and a separate retention latch that maintains data independently. This segmentation allows the data storage function to be separated from the power-consuming logic circuitry, enabling power cutoff without data loss.
Solution Approach 2:
The retention latch acts as an intermediary between the powered-off flip-flop and the external system. It holds the data in a preserved state during power-down modes and can restore the flip-flop to its previous state when power is resumed, thereby mediating the data loss problem caused by power cutoff.
3Reliability
If a retention latch is added to maintain data during power-down mode, then data retention is improved, but device complexity increases
Solution Approach 1:
The retention latch is designed with multi-functionality to minimize complexity. It serves multiple purposes: holding data during power-down, restoring the flip-flop state upon power-up, and being controllable through existing control signals (reset and set signals). By making the retention latch universal in its functionality, the patent avoids adding excessive complexity while achieving reliable data retention.
Data Source
AI summary
A retention flip-flop includes a master latch outputting a first signal which is generated based on a signal inputted through an input terminal based on first control signals; a slave latch outputting a second signal generated based on the first signal based on the first control signals and second control signals; and a control logic that generates the first control signals based on a clock signal and provides the first control signals to the master latch and the slave latch, and generates the second control signals based on a power down signal and provides the second control signals to the slave latch. The slave latch comprises a retention latch which transmits the first signal to an output terminal as the second signal by operating as an open loop based on the second control signals or maintains the second signal by forming a closed loop based on the second control signals.