Slave Module Wake-Up Signal Propagation

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Solution Overview

Problem

In high-capacity battery systems, existing technologies face challenges in efficiently propagating wake-up signals across multiple slave modules to ensure all modules are properly activated and managed, leading to potential inefficiencies and incomplete data collection.

Innovation Solution

A slave module design that includes an analog front end (AFE) and a processor to receive a first wake-up signal, output a voltage, and transmit a second wake-up signal to adjacent modules, utilizing communication lines and isolators to ensure reliable signal propagation and module activation, with shielded cables for noise protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wake-up signals are propagated sequentially through multiple slave modules, then all modules can be activated, but the activation time and signal propagation delay increase

Engineering Contradiction:
Improvemodule activation reliabilityVSAvoidwake-up signal propagation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system divides the wake-up signal propagation into segments, where each slave module acts as an intermediate node that receives the signal from the previous module and re-transmits it to the next module. This segmentation allows the signal to propagate through the chain of modules in an organized manner, ensuring reliable activation while managing the time delay through structured signal handling at each node.

Inventive Principle:
Principle #1Segmentation

2Use of energy by moving object

If slave modules remain in sleep mode to save energy, then energy consumption is reduced, but the system response time increases when wake-up is needed

Engineering Contradiction:
Improveslave module energy consumptionVSAvoidsystem response speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The slave modules are pre-configured with the capability to receive and process wake-up signals while in sleep mode. The AFE and processor are designed to be in a low-power state but remain capable of detecting the wake-up signal, allowing the system to maintain energy efficiency while being prepared for rapid activation when needed.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If multiple slave modules are connected in a chain for signal propagation, then all modules can be managed centrally, but signal interference and noise increase

Engineering Contradiction:
Improvecentralized module managementVSAvoidsignal interference and noise
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

Each slave module serves as an intermediary in the signal propagation chain, receiving the wake-up signal from the previous module and re-transmitting it to the next module. This intermediary approach allows the signal to be managed and potentially regenerated at each node, reducing the cumulative effect of noise and interference that would occur in a direct long-distance connection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10785054B2Slave module
Publication Date: 2020.09.22 SAMSUNG SDI CO LTD
  • US10785054B2 patent drawing
  • US10785054B2 patent drawing
  • US10785054B2 patent drawing

AI summary

A slave module receives a first wake-up signal from an adjacent previous module to perform a wake-up operation and to transmit a second wake-up signal to an adjacent subsequent module. The slave module includes: an analog front end (AFE) including a first terminal and a second terminal, the AFE may be woken up by receiving the first wake-up signal through the first terminal and may output a first voltage through the second terminal in a woken up state; a processor including a third terminal electrically connected to the first terminal, a fourth terminal electrically connected to the second terminal, and a fifth terminal electrically connected to a second slave terminal. The processor may boot up when the first voltage is applied to the fourth terminal, may output a second voltage to the third terminal after being booted up, and may output the second wake-up signal to the fifth terminal.