Slave Side Bus Arbiter for Reducing Idle Time

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Solution Overview

Problem

In computer systems, concurrent bus access requests from multiple master devices to the same slave device lead to inefficiencies due to time-multiplexing, resulting in increased slave device idle time and reduced system performance.

Innovation Solution

Implementing a slave side arbiter that maintains the selection of a master port for at least one additional bus cycle after a transfer, preventing the slave device from entering an idle state and allowing for continuous bus connections, thereby reducing idle time and enhancing system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If time-multiplexing is used to manage concurrent bus access requests, then bus access control is simplified, but slave device idle time increases and system performance decreases

Engineering Contradiction:

Improvebus access controlVSAvoidsystem performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The arbiter maintains the master port selection for at least one additional bus cycle after the transfer completes, proactively preventing idle time before it occurs. This preliminary action of extending the selection ensures continuous bus connection readiness, eliminating the need for re-arbitration and improving system performance without complicating the control mechanism.

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If master port selection is maintained for additional bus cycle(s), then slave device idle time is reduced, but arbiter complexity increases

Engineering Contradiction:

Improveslave device idle timeVSAvoidarbiter complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The arbiter changes the temporal parameter of master port selection by extending it for at least one additional bus cycle beyond the transfer completion. This parameter change from immediate release to extended maintenance simplifies the overall system behavior by ensuring continuous bus availability, reducing idle time without requiring complex arbitration logic.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If bus transfer time-multiplexing is implemented, then concurrent access is managed, but data transfer efficiency decreases

Engineering Contradiction:

Improveconcurrent access managementVSAvoiddata transfer efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The arbiter ensures continuous bus connection by maintaining the master port selection for at least one additional bus cycle after transfer completion. This continuity prevents bus idle time and ensures the bus remains available for immediate next transfers, significantly improving data transfer efficiency while preserving concurrent access management capabilities.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS9798686B2Slave side bus arbitration

Publication Date: 2017.10.24 SILICON LABORATORIES INC

AI summary

A method includes, in response to a master port requesting bus access for a bus transfer with a slave port, selecting the master port to allow a master device that is coupled to the master port to perform a bus transfer with a slave device that is coupled to the slave port. The bus transfer is associated with at least one bus cycle. The method includes, in response to an end of the bus transfer, maintaining selection of the master port for at least one additional bus cycle.