SLC Buffer Control for MLC Storage Read Write Speed

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Solution Overview

Problem

Storage systems face challenges in improving read and write performance due to the slower read speeds of multi-level cell (MLC) blocks compared to single-level cell (SLC) blocks, and existing solutions like WriteBooster and ReadBooster have limitations in optimizing data transfer and memory usage.

Innovation Solution

Implementing read and write booster buffer control modules that store data from MLC blocks in SLC blocks as a buffer, allowing for improved read performance by pre-reading data from MLC blocks into SLC blocks before an official read command is received, and managing write buffer retention to reduce unnecessary data transfer and energy waste.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If MLC blocks are used for storage, then cost is reduced, but read and write speed deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidread and write speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The storage system is segmented into two distinct buffer types: a first buffer for read operations and a second buffer for write operations. This segmentation allows each buffer to be optimized for its specific function, with the first buffer using faster memory for read operations and the second buffer managing write operations separately, thereby resolving the speed penalty of MLC blocks while maintaining cost efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary buffer memory as a mediator between the MLC storage blocks and the host system. This intermediary layer caches frequently accessed data, allowing fast read operations without directly accessing the slower MLC blocks, thus resolving the speed limitation while preserving the cost benefits of MLC storage.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If data is transferred frequently between buffers and MLC blocks, then access speed is improved, but energy consumption increases

Engineering Contradiction:
Improvedata access speedVSAvoidenergy consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The system performs preliminary actions by pre-loading data into the first buffer before actual read requests are made, and by maintaining write data in the second buffer ready for efficient transfer. This preliminary preparation reduces the frequency and intensity of data transfers during normal operation, thereby improving access speed while reducing overall energy consumption.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically changes operational parameters such as buffer allocation sizes, data retention times in buffers, and transfer timing based on access patterns. By adjusting these parameters, the system optimizes the balance between transfer frequency (affecting speed) and total data movement (affecting energy consumption), resolving the contradiction between speed and energy use.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11675512B2Storage system and method for using read and write buffers in a memory
Publication Date: 2023.06.13 SANDISK TECHNOLOGIES LLC
  • US11675512B2 patent drawing
  • US11675512B2 patent drawing
  • US11675512B2 patent drawing

AI summary

A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.