Single Level Cell Buffering for Non-Volatile Memory Leakage
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Solution Overview
Problem
Multiple level cell (MLC) non-volatile memory devices face challenges with floating gate to floating gate coupling along the same bit line, leading to reduced voltage margins and potential errors in reading data due to current leakage.
Innovation Solution
Incorporating single level cells (SLCs) between multiple level cells (MLCs) and select gates to reduce voltage differences and prevent current leakage, with additional word lines used to maintain memory block uniformity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple level cells (MLCs) are used to increase memory density, then memory capacity per cell increases, but voltage margins between adjacent gates decrease and current leakage increases
Solution Approach 1:
Single level cells (SLCs) are inserted as intermediary cells between MLCs and select gates. These SLCs act as voltage buffers that reduce the potential difference between high-voltage MLCs and low-voltage select gates, preventing direct coupling and charge leakage while maintaining the high density benefits of MLC architecture
Solution Approach 2:
The memory array is segmented into alternating sequences of SLCs and MLCs rather than using uniform cell types. This segmentation creates a pattern where SLCs are positioned at critical locations (between MLCs and select gates, and between MLCs and bit lines) to provide electrical isolation and prevent coupling, while MLCs provide high density in the bulk of the array
2Quantity of substance
If multiple level cells (MLCs) are used to increase memory density, then memory capacity per cell increases, but charge leakage between adjacent gates increases
Solution Approach 1:
SLCs serve as intermediary buffer cells that reduce the voltage differential between MLCs and select gates/bit lines. By inserting these intermediate cells with intermediate voltage levels, direct charge leakage paths are broken, reducing energy loss while preserving the high storage capacity of MLCs
Solution Approach 2:
The potential difference between MLCs and select gates, which originally causes harmful charge leakage, is converted into a beneficial voltage gradient by inserting SLCs. The SLCs are programmed to intermediate voltage levels that create controlled voltage steps, transforming the harmful direct coupling into a managed voltage transition that prevents leakage
3Stability of the object's composition
If additional word lines are added to maintain memory block uniformity, then block uniformity is improved, but device complexity increases
Solution Approach 1:
The memory array is divided into uniform blocks containing alternating SLC-MLC sequences. Each block is designed with consistent voltage characteristics and coupling patterns, allowing standardized control logic. The segmentation into uniform blocks simplifies control despite the alternating cell types, as each block can be managed with identical procedures
Solution Approach 2:
The invention changes the voltage parameters applied to different word lines based on their position in the SLC-MLC sequence. By adjusting voltage levels dynamically according to the cell type and position, uniform operation across the entire array is achieved without requiring additional physical word lines, managing complexity through parameter variation rather than structural expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases memory density while reducing read errors and charge leakage, maintaining memory stability and block uniformity by shielding high-potential MLCs from adjacent low-potential select gates.
Implementation Method 1
marked potential differences between adjacent gates... coupling can be induced by marked potential differences
Data Source
AI summary
Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells.