SLC Cache Write Completion Timing for Stable QLC Memory Rates
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Solution Overview
Problem
Existing memory sub-systems lack adequate control mechanisms for data transfer rates, leading to significant variance and unwanted latency, particularly in systems using Quad-Level Cell (QLC) memory, which affects host system performance.
Innovation Solution
Implementing a memory sub-system with single-level cell memory caching and dynamic rate control, utilizing a processing logic to adjust target data rates based on free space and host bandwidth, and employing a gear-based approach to maintain consistent performance by controlling the host-to-cache, cache-to-data, and data-to-data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If QLC memory is used to increase storage capacity, then storage density is improved, but write speed and performance deteriorate
Solution Approach 1:
The memory sub-system is divided into two distinct bands: a cache band using SLC memory for high-speed writes and a data band using QLC memory for high-density storage. This segmentation allows the system to leverage the advantages of both memory types - fast writes to SLC cache and high capacity to QLC storage - thereby resolving the contradiction between storage capacity and write speed.
Solution Approach 2:
The SLC cache band acts as an intermediary between the host system and the QLC data band. Host writes are first buffered in the fast SLC cache, then asynchronously flushed to the QLC data band. This intermediary mechanism decouples the host write rate from the QLC write rate, allowing high-speed writes to be buffered while QLC writes proceed at its own pace, thus maintaining both speed and capacity.
2Productivity
If data transfer rate is increased to improve performance, then bandwidth is improved, but latency and data loss increase
Solution Approach 1:
The system dynamically adjusts the host-to-cache write rate based on real-time conditions including cache free space, data band write rate, and host bandwidth. This dynamic rate control prevents the host from writing too fast and causing data loss or excessive latency, while still allowing high bandwidth when conditions permit. The adaptive mechanism resolves the contradiction by making the transfer rate flexible rather than fixed.
Solution Approach 2:
The rate control mechanism continuously monitors system state (cache occupancy, data band status, host bandwidth) and uses this feedback to adjust the host-to-cache write rate. This closed-loop feedback ensures that bandwidth is maximized when possible while preventing latency and data loss when the system is constrained, thus resolving the contradiction between high bandwidth and low latency.
3Productivity
If host writes data at high rate to improve productivity, then write throughput is improved, but cache overflow and data loss occur
Solution Approach 1:
The system performs preliminary actions by maintaining a buffer in the SLC cache band that can temporarily hold data before it is flushed to the QLC data band. This buffer capacity allows the host to write at high rates without immediate data loss, as the cache can absorb transient spikes in write throughput. The preliminary buffering action prevents data loss while maintaining high productivity.
Solution Approach 2:
The system changes the effective write rate parameter dynamically by adjusting the host-to-cache rate based on cache free space and data band status. When the cache is nearly full or the data band is slow, the system reduces the host write rate to prevent overflow. This parameter adjustment ensures reliability by preventing data loss while maintaining high throughput when conditions allow.
4Stability of the object's composition
If rate control is implemented to reduce latency, then performance consistency is improved, but system complexity increases
Solution Approach 1:
The rate control mechanism is self-managing, using the memory sub-system's own internal state (cache occupancy, data band status) to automatically adjust host write rates. The system serves itself by monitoring its own conditions and making appropriate rate adjustments without external intervention. This self-service approach improves performance consistency while minimizing the operational complexity, though the underlying control logic remains in place.
Data Source
AI summary
Processing logic in a memory sub-system receives, from a host system, a plurality of write commands for writing data to the memory device. Upon writing the data to a cache of the memory device, the processing logic generates a plurality of completion entries, the plurality of completion entries corresponding to the plurality of write commands and comprising respective timestamps, wherein the respective timestamps are based on a target host-to-cache data rate, and sends the plurality of completion entries to the host system based on the respective timestamps.