All String Verify Mode for SLC Memory Fault Detection
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Solution Overview
Problem
Existing non-volatile memory technologies, particularly SLC memory, face challenges in detecting faulty strings during programming due to incomplete verification processes, leading to undetected errors and reduced reliability.
Innovation Solution
A programming scheme that verifies multiple strings in parallel after programming, ensuring all strings are checked for data states, using a control circuit with a programming, counting, and determination circuit to identify faulty blocks by analyzing the number of sets in a specific data state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification is performed for all strings in parallel, then detection of faulty strings is improved, but device complexity increases due to additional counting and determination circuits
Solution Approach 1:
The verification process is segmented into distinct functional blocks: a programming circuit for parallel string programming, a counting circuit for tallying verified sets, and a determination circuit for faulty block identification. This segmentation allows each component to perform a specific function efficiently, improving overall reliability without requiring a complete redesign of the verification system.
Solution Approach 2:
The counting circuit serves as an intermediary between the parallel verification process and the final determination of faulty blocks. It accumulates verification results from multiple strings and translates them into a format that the determination circuit can process, thereby managing the complexity of parallel verification without directly increasing the complexity of the final decision-making process.
2Manufacturing precision
If all memory cells are verified in parallel, then programming accuracy is improved, but programming time increases due to additional verification steps
Solution Approach 1:
The verification process is implemented as a periodic operation that occurs after programming phases. The memory device alternates between programming multiple strings in parallel and performing verification on completed sets, allowing high-speed programming to proceed without continuous verification overhead while still ensuring accuracy through systematic periodic checks.
Solution Approach 2:
The parallel verification process operates continuously on multiple strings simultaneously, ensuring that verification activity is maintained without idle periods. By verifying multiple sets in parallel rather than sequentially, the system maintains high utilization of verification resources while completing all necessary checks, thereby minimizing the time penalty associated with verification.
Data Source
AI summary
A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.