SLC Memory Voltage Control for Write Speed
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Solution Overview
Problem
As memory cells age and undergo numerous program/erase cycles, their performance degrades, leading to increased errors during programming and reading, which can render the proposed deeper erase and weaker program processes less effective, necessitating an adaptive approach to maintain high performance.
Innovation Solution
A control circuit monitors the number of program/erase cycles and adjusts the threshold voltage ranges for programming and erasing, implementing a deeper erase and weaker program process for SLC memory cells, thereby optimizing performance by changing the voltage distributions based on the cell's operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If deeper erase and weaker program processes are used for SLC memory cells, then programming and sensing voltages are reduced and operation times are shortened, but performance degrades after numerous program/erase cycles leading to increased errors
Solution Approach 1:
The patent implements dynamic adjustment of voltage ranges based on the operating condition (number of program/erase cycles) of the memory cells. The control circuit monitors the age of memory cells and adapts the erase and program voltage ranges accordingly, transitioning from fixed voltage ranges to dynamic, condition-based voltage ranges to maintain reliability while preserving speed benefits.
Solution Approach 2:
The patent changes the voltage parameters (erase voltage range and program voltage range) based on the operating condition of the memory cells. For younger cells, wider voltage ranges are used to maintain reliability, while for older cells, adjusted voltage ranges are applied to compensate for degradation, thereby maintaining both speed and reliability across the device lifecycle.
2Device complexity
If fixed voltage ranges are used for programming and erasing SLC memory cells, then the process is simple, but performance degrades over time due to not adapting to cell aging
Solution Approach 1:
The patent incorporates a feedback mechanism where the control circuit monitors the operating condition (number of program/erase cycles) of the memory cells and uses this information to adjust the voltage ranges dynamically. This feedback loop enables the system to adapt to cell aging and maintain consistent performance without requiring complex external intervention.
Solution Approach 2:
The memory system performs self-adjustment by automatically monitoring its own operating conditions and adapting the voltage ranges accordingly. The control circuit within the system itself manages the adaptation process, eliminating the need for external calibration or manual intervention, thereby maintaining simplicity while improving reliability.
3Reliability
If adaptive voltage range adjustment is implemented based on program/erase cycle count, then reliability is maintained over time, but device complexity increases
Solution Approach 1:
The memory system performs self-adjustment by automatically monitoring its own operating conditions and adapting the voltage ranges accordingly. The control circuit within the system itself manages the adaptation process, eliminating the need for external calibration or manual intervention, thereby maintaining simplicity while improving reliability.
Solution Approach 2:
The patent changes the voltage parameters (erase voltage range and program voltage range) based on the operating condition of the memory cells. For younger cells, wider voltage ranges are used to maintain reliability, while for older cells, adjusted voltage ranges are applied to compensate for degradation, thereby maintaining both speed and reliability across the device lifecycle.
Data Source
AI summary
A storage system comprises a controller connected to blocks of non-volatile memory cells. The memory cells can be operated as single level cell (“SLC”) memory cells or multi-level cell (“MLC”) memory cells. To increase write performance for a subset of memory cells being operated as SLC memory cells, the controller performs a deeper erase process and a weaker program process for the subset of memory cells. The weaker program process results in a programmed threshold voltage distribution that is lower than the “nominal” programmed threshold voltage distribution. Having a lower programmed threshold voltage distribution reduces the magnitude of the programming and sensing voltages needed and, therefore, shortens the time required to generate the programming and sensing voltages, and reduces power consumption.