Single Level Cell Programming in MLC Memory Arrays
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Solution Overview
Problem
Non-volatile memory devices, particularly those using multiple level cells (MLC), face challenges with floating gate-to-floating gate capacitive coupling causing program disturb conditions and reduced reliability due to the need for tight threshold voltage control, which complicates increasing memory density while maintaining reliability.
Innovation Solution
A method for programming a multiple level non-volatile memory device in single level cell mode by writing data to either the least significant bit or most significant bit and using reinforcing data to adjust the threshold level, reducing interference and enhancing reliability through scrambled logical addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple level cells are used to increase memory density, then the amount of data stored per cell increases, but floating gate-to-floating gate capacitive coupling causes program disturb conditions that reduce reliability
Solution Approach 1:
The patent segments the programming operation into two distinct phases: a first programming phase that programs one bit (LSB or MSB) and a second programming phase that programs the remaining bit. This segmentation allows the system to achieve MLC density while using SLC programming techniques in the first phase, thereby reducing program disturb conditions and improving reliability while maintaining high memory density.
2Quantity of substance
If multiple level cells are used to increase memory density, then the amount of data stored per cell increases, but tight control of threshold voltages is required which complicates the system
Solution Approach 1:
The patent divides the programming process into two phases where the first phase programs only one bit (either LSB or MSB) without requiring tight threshold voltage control. This segmentation relaxes the threshold voltage control requirements compared to traditional MLC programming, thereby increasing memory density without proportionally increasing device complexity.
Solution Approach 2:
The patent performs preliminary programming of one bit (LSB or MSB) in the first programming phase before completing the programming of the remaining bit. This preliminary action establishes a foundation that simplifies the subsequent programming phase and reduces the overall complexity of threshold voltage control required for MLC operation.
3Reliability
If reinforcing data is used to adjust threshold levels, then reliability is enhanced, but additional programming operations are required
Solution Approach 1:
The patent segments the programming operation into two distinct phases: a first programming phase that programs one bit and a second programming phase that programs the remaining bit with reinforcing data. This segmentation enhances reliability by ensuring proper threshold voltage adjustment while managing programming time through efficient phase organization.
Solution Approach 2:
The patent performs preliminary programming of one bit in the first phase, which establishes a foundation that simplifies and accelerates the second programming phase. This preliminary action reduces the overall programming time compared to traditional MLC programming by avoiding the need for multiple iterative adjustments.
Data Source
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AI summary
A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell . A second programming operation then programs reinforcing data that adjusts the threshold level of the cell to the appropriate level for the desired data.