Flash Memory RAID-Like Parity Transfer from SLC to MLC Blocks
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Solution Overview
Problem
Conventional flash memory controllers inefficiently utilize memory space by dedicating one eighth of a data block for parity check codes, reducing the effective storage capacity and user experience due to high error rates during programming.
Innovation Solution
Implementing a RAID-like error correction code encoding operation in a flash memory apparatus, which classifies data into groups and uses XOR encoding to generate parity check codes, allowing for internal copying and error correction across single-level-cell and multiple-level-cell blocks, thereby reducing the need for excessive parity check codes and improving data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory controllers program parity check codes into dedicated memory pages, then error correction capability is improved, but memory space utilization deteriorates
Solution Approach 1:
The patent merges data pages and parity check code pages into a unified storage structure. Instead of dedicating separate pages for parity codes, the system interleaves parity codes within data pages, allowing simultaneous storage of both data and error correction codes in the same memory space, thereby improving space utilization while maintaining error correction capability
Solution Approach 2:
The patent makes memory pages serve multiple functions - they can store data, parity check codes, or both simultaneously depending on the programming mode. This multi-functionality allows the same memory resource to be flexibly allocated for different purposes, resolving the contradiction between dedicated parity storage and space utilization
2Reliability
If one eighth of memory space is allocated for parity check codes, then error correction capability is improved, but effective storage capacity deteriorates
Solution Approach 1:
The patent changes the parameter of parity code allocation from a fixed one-eighth ratio to a flexible allocation scheme. By dynamically adjusting the amount and location of parity codes based on data patterns and error probability, the system achieves adequate error correction with less than 12.5% overhead, thereby increasing effective storage capacity
3Reliability
If parity check codes are programmed into every data block, then error correction capability is improved, but programming complexity deteriorates
Solution Approach 1:
The patent segments the memory into different types (SLC and MLC) and applies different parity coding strategies to each segment. SLC blocks use simpler parity schemes while MLC blocks use more robust coding, reducing overall programming complexity compared to applying a uniform complex scheme to all blocks
Data Source
AI summary
A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.