SLC Read Disturb Indicator Pages for NAND Memory

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Solution Overview

Problem

Current NAND memory devices face inefficiencies in monitoring for read disturb errors due to the coarse granularity of error counters and the limitations of using dummy memory cells, which require extensive scanning and can be prone to defects.

Innovation Solution

Implementing higher read-margin cell types such as SLC or MLC cells as read disturb indicators, which have greater tolerance to read disturb current leakage, allowing for more granular monitoring and reducing the time required for read disturb scans by scanning fewer pages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dummy memory cells are used for read disturb detection, then read disturb errors can be monitored, but the scanning process requires extensive time and resources

Engineering Contradiction:
Improveread disturb error detectionVSAvoidscan time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the read disturb detection function from the main data storage function by using dedicated indicator pages within the data pages themselves. These indicator pages contain specific memory cells (e.g., cells at predetermined addresses or cells with specific data patterns) that serve solely as indicators for read disturb conditions, allowing detection without scanning entire pages.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the monitoring function by dividing memory pages into data portions and indicator portions. The indicator pages are further segmented into specific indicator cells that are monitored for read disturb conditions. This segmentation allows selective monitoring of only the critical indicator cells rather than scanning all cells in a page, significantly reducing scan time while maintaining detection capability.

Inventive Principle:
Principle #1Segmentation

2Reliability

If dummy memory cells are used for read disturb monitoring, then error detection is possible, but the device complexity increases

Engineering Contradiction:
Improveread disturb error detectionVSAvoidmonitoring structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the indicator pages serve multiple functions: they act as both data storage pages (capable of holding user data) and as read disturb indicator pages. The same physical memory structure is used for both data storage and error indication, eliminating the need for separate dummy memory cells or dedicated monitoring structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the data storage function and the read disturb indication function into the same memory structure. Indicator pages are integrated within the data pages, and indicator cells are part of the regular memory array. This merging eliminates the need for separate monitoring hardware or structures, reducing device complexity while maintaining detection capability.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If higher read-margin cell types (SLC or MLC) are used as read disturb indicators, then detection precision is improved, but the quantity of cells required increases

Engineering Contradiction:
Improveread disturb detection precisionVSAvoidnumber of indicator cells
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent applies partial monitoring by selecting only specific cells within indicator pages as read disturb indicators. Rather than monitoring all cells in indicator pages, the patent monitors only predetermined cells (e.g., cells at specific addresses or cells containing specific data patterns). This partial action provides sufficient detection precision while minimizing the number of cells that need to be monitored.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11688473B2SLC page read
Publication Date: 2023.06.27 MICRON TECHNOLOGY INC
  • US11688473B2 patent drawing
  • US11688473B2 patent drawing
  • US11688473B2 patent drawing

AI summary

NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.