NAND SLC Sub-Block Read Refresh for Read Disturb Control

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Solution Overview

Problem

Conventional NAND memory devices suffer from low bandwidth and high power consumption, making them unsuitable alternatives to high bandwidth memory (HBM) devices, particularly in applications requiring high data access rates like large language models.

Innovation Solution

Implementing a high bandwidth flash (HBF) package with sub-blocks having different read usage thresholds based on memory cell vulnerability to read disturb, allowing for targeted read refresh operations to enhance performance and longevity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional NAND memory devices are used, then cost is reduced compared to HBM, but bandwidth is insufficient and power consumption is too high

Engineering Contradiction:
ImprovebandwidthVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The memory block is divided into multiple sub-blocks (first sub-block, second sub-block, third sub-block, fourth sub-block) with different read usage thresholds. This segmentation allows selective refresh operations on specific sub-blocks based on their individual read cycle counts, enabling targeted power management while maintaining overall high bandwidth performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic read usage thresholds for different sub-blocks that can be adjusted based on read disturb vulnerability. The thresholds are not fixed but adapt to the specific characteristics of each sub-block, allowing the system to optimize between bandwidth and power consumption dynamically based on actual usage patterns and vulnerability profiles.

Inventive Principle:
Principle #15Dynamics

2Speed

If read operations are performed frequently on vulnerable sub-blocks, then data access performance is improved, but read disturb errors increase

Engineering Contradiction:
Improvedata access rateVSAvoiddata retention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent performs preliminary classification of sub-blocks into different read disturb vulnerability categories before normal operation. Based on this pre-assessment, different read usage thresholds are assigned to different sub-blocks. This preliminary action prevents read disturb errors by proactively limiting read operations on vulnerable sub-blocks before damage occurs, while still allowing high-speed access to resilient sub-blocks.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system continuously monitors read cycle counts for each sub-block and compares them against the predetermined thresholds. When a sub-block's read cycle count approaches its threshold, the system provides feedback to limit further read operations on that sub-block. This closed-loop feedback mechanism dynamically balances data access performance with data retention reliability.

Inventive Principle:
Principle #23Feedback

3Device complexity

If uniform read usage thresholds are applied to all sub-blocks, then device complexity is reduced, but read disturb vulnerability is not adequately addressed

Engineering Contradiction:
Improvethreshold managementVSAvoidread disturb protection
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

Instead of applying a uniform read usage threshold across all sub-blocks, the patent assigns different thresholds to different sub-blocks based on their local characteristics and read disturb vulnerability. Each sub-block receives a tailored threshold that matches its specific tolerance level, providing localized optimization rather than a one-size-fits-all approach. This resolves the contradiction by accepting increased complexity in threshold management as necessary for achieving reliable read disturb protection.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250378891A1SLC sub-block mode for nonvolatile memory devices
Publication Date: 2025.12.11 SANDISK TECHNOLOGIES LLC
  • US20250378891A1 patent drawing
  • US20250378891A1 patent drawing
  • US20250378891A1 patent drawing

AI summary

The memory device includes a memory block with an array of memory cells that are arranged in word lines that are divided into sub-blocks, each of which is associated with an individual read usage threshold. Control circuitry is configured to program the memory cells of the word lines to include data and to perform a plurality of read operations on the word lines of the plurality of sub-blocks and compare a read usage metric associated with a selected sub-block of the plurality of sub-blocks to the read usage threshold that is associated with the selected sub-block. In response to the read usage metric exceeding the read usage threshold, the control circuitry is configured to perform a read refresh operation on the selected sub-block. The individual read usage thresholds associated with the sub-blocks are based on vulnerabilities of the memory cells in the sub-blocks to read disturb.