Nonvolatile Memory Controller Switching SLC and TLC Modes
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Solution Overview
Problem
The lifespan of nonvolatile memory devices, such as flash memory, is limited due to excessive erasure operations, which is exacerbated by write amplification issues and the need for efficient storage capacity management.
Innovation Solution
A data storage device with a microcontroller that switches between single level cell (SLC) and triple level cell (TLC) writing modes based on accumulated data amounts and spare block availability, using judgment formulas to optimize block allocation and reduce erase count, thereby extending the device's lifespan and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is continuously written to nonvolatile memory blocks, then storage capacity is utilized, but the number of erasure operations increases and block lifespan decreases
Solution Approach 1:
The patent implements dynamic switching between SLC and TLC writing modes based on real-time monitoring of accumulated write data amounts and spare block availability. This dynamic adaptation allows the system to optimize between storage capacity utilization and block lifespan preservation by selecting the appropriate writing mode according to current operational conditions
Solution Approach 2:
The system changes operational parameters by switching between different writing modes (SLC vs. TLC) with distinct characteristics. SLC mode offers higher reliability and longer block lifespan with lower erasure tolerance, while TLC mode provides higher storage capacity utilization but requires more frequent erasures. The microcontroller adjusts the writing mode parameter based on accumulated data amounts and spare block conditions
2Reliability
If SLC writing mode is used to extend block lifespan, then erasure count is reduced, but storage capacity utilization decreases
Solution Approach 1:
The system dynamically transitions between SLC and TLC modes rather than statically committing to one approach. When spare blocks are充足 and accumulated write data reaches certain thresholds, the system switches to TLC mode to maximize storage capacity utilization. When spare blocks are depleted or reliability concerns arise, it switches back to SLC mode to preserve block lifespan
Solution Approach 2:
The patent makes the nonvolatile memory system multi-functional by enabling it to operate in both SLC and TLC modes. This universality allows the same physical memory blocks to serve dual purposes: preserving lifespan through SLC operations when needed, and maximizing capacity utilization through TLC operations when conditions permit
3Productivity
If TLC writing mode is used to maximize storage capacity, then storage efficiency increases, but erasure operations increase and reliability decreases
Solution Approach 1:
The microcontroller monitors accumulated write data amounts in TLC mode and switches to SLC mode when thresholds are exceeded. This parameter change approach allows the system to achieve high storage efficiency during TLC operations while preventing reliability degradation by transitioning to the more conservative SLC mode when erasure tolerance becomes critical
Solution Approach 2:
The system implements feedback control by continuously monitoring the accumulated amount of data written in each mode and the number of spare blocks available. Based on this feedback, the microcontroller makes intelligent decisions about when to switch between modes, ensuring that TLC mode is used to maximize storage efficiency only when conditions permit, and SLC mode is activated when reliability concerns arise
Data Source
AI summary
Optimized writing techniques for nonvolatile memory are presented. A microcontroller switches between a first writing mode and a second writing mode to write data to the nonvolatile memory. The switching between the first writing mode and the second writing mode depends on a first accumulated amount of data written to the nonvolatile memory in the first writing mode, or a number of spare blocks of the nonvolatile memory that is evaluated after a garbage collection procedure.