Self-Aligned Gate SLCFET Drain Ledge Misalignment
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Solution Overview
Problem
Conventional superlattice castellated field effect transistor (SLCFET) devices experience performance variability due to varying source and drain access region lengths caused by gate misalignment, leading to adverse impacts on device performance.
Innovation Solution
A self-aligned gate structure is introduced, featuring a continuous gate metal coverage over source-side multichannel ridges and trenches, with a drain ledge to accommodate misalignment, eliminating source-side castellations and optimizing channel and drain castellations separately for improved linearity and dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional superlattice castellations are used with gate metal deposition, then the device structure is formed, but source and drain access region lengths vary due to gate misalignment causing performance variability
Solution Approach 1:
The patent introduces a ledge structure formed before gate metal deposition that pre-defines the boundary between the channel region and drain access region. This preliminary structural feature ensures that regardless of gate alignment variations, the drain access region length remains consistent, eliminating performance variability caused by misalignment.
Solution Approach 2:
The ledge acts as an intermediary element between the channel region and drain access region. It provides a reference structure that mediates the relationship between the gate and the castellations, ensuring that the drain access region length is determined by the ledge position rather than gate alignment, thus maintaining consistency.
2Ease of manufacture
If gate metal is deposited to cover castellations, then channel region is defined, but source and drain access region lengths vary depending on gate alignment
Solution Approach 1:
The patent extracts the function of defining access region boundaries from the gate metal deposition process. By introducing the ledge structure, the boundary definition is separated from gate alignment, allowing gate deposition to proceed without requiring high precision alignment while still maintaining controlled access region lengths.
3Productivity
If superlattice castellations extend beyond gate length, then channel region is formed, but source and drain access regions have varying lengths causing adverse impact on device performance
Solution Approach 1:
The ledge structure is formed preliminarily to establish fixed boundaries for the drain access region. This allows the superlattice castellations to extend beyond the gate length as needed for channel formation, while the ledge ensures consistent drain access region length independent of gate alignment, maintaining device performance.
Data Source
AI summary
A transistor device comprises a base structure and a superlattice of conducting channels overlying the base structure. The superlattice of conducting channels includes source and drain access regions spaced-apart from each other, a ledge between and spaced-apart from the source and drain access regions, and source-side alternating multichannel ridges and trenches that extend from the source access region to the ledge, each ridge having a topside and opposing sidewalls that each extend from the ledge to the source access region. The transistor device includes gate metal that covers each ridge continuously from the ledge to the source access region, such that the gate metal completely covers the topside of the ridge and edges of the conducting channels that intersect the sidewalls of the ridge.