Multichannel SLCFET Modulated Doping for On-Resistance and Breakdown Voltage
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Solution Overview
Problem
Multichannel devices, such as SLCFETs, face limitations in breakdown and pinch-off voltage due to high electric fields and non-uniformity in sidewall slopes during etching, leading to increased on-state resistance and potential device breakdown.
Innovation Solution
The implementation of modulated doping techniques to vary carrier concentration across channels and thickening of certain channel epitaxial layers to optimize pinch-off voltage and reduce electric field effects, combined with a castellated gate structure that surrounds the multichannel ridges, to achieve uniform pinch-off and lower on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple heterostructure layers are stacked to increase current flow, then on-resistance decreases, but breakdown voltage decreases due to high electric fields
Solution Approach 1:
The patent applies local quality by varying the doping concentration in specific barrier layers (e.g., higher doping in lower barrier layers, lower doping in upper barrier layers) to create non-uniform carrier concentration profiles across the multichannel structure. This localized modification allows different regions to have optimized properties: lower channels have higher carrier concentration for better conduction, while upper channels have lower carrier concentration to reduce electric field intensity and prevent premature breakdown, thus resolving the contradiction between low on-resistance and high breakdown voltage
Solution Approach 2:
The patent changes physical parameters by modulating the doping concentration (carrier concentration) across different heterostructure layers. By adjusting the doping levels in barrier layers and consequently the carrier concentration in each channel, the patent optimizes both the on-resistance (through sufficient carrier density) and breakdown voltage (by limiting carrier concentration in high-field regions), thereby resolving the trade-off between these two critical parameters
2Ease of manufacture
If ridges are etched with sloped sidewalls due to fabrication limits, then manufacturing is easier, but pinch-off voltage becomes non-uniform across channels
Solution Approach 1:
The patent applies local quality by implementing position-dependent doping concentrations in the barrier layers. Lower barrier layers (affecting lower channels) have higher doping concentrations to compensate for the wider effective channel width caused by sloped sidewalls, while upper barrier layers have lower doping concentrations. This localized adjustment ensures that each channel achieves approximately uniform pinch-off voltage despite the non-uniform ridge geometry, resolving the contradiction between ease of manufacture and manufacturing precision
3Length of moving object
If gate to ridge distance is reduced to 5-20 nm for standard FETs, then pinch-off voltage is small, but this geometry cannot be achieved in sidewall gate structures
Solution Approach 1:
The patent changes the carrier concentration parameter in the barrier layers to compensate for the larger gate-to-channel distance in sidewall gate structures. By increasing the doping concentration in barrier layers adjacent to lower channels, the patent increases the carrier density in those channels, which enhances the electrostatic control and reduces the effective pinch-off voltage despite the larger physical distance. This parameter modification allows sidewall gate structures to achieve pinch-off characteristics comparable to top-gate structures, resolving the contradiction between geometry constraints and voltage control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables SLCFETs to support higher voltage and power modes while maintaining low on-state resistance, reducing the necessary pinch-off voltage and enhancing device linearity and transconductance.
Implementation Method 1
Certain heterostructure materials, such as Aluminum Gallium Nitride (AlGaN) and GaN, create an electron well (i.e., a sheet of electrons) at the interface between the two dissimilar materials resulting from the piezoelectric effect and spontaneous polarization effect therebetween.
Implementation Method 2
Certain heterostructure materials, such as Aluminum Gallium Nitride (AlGaN) and GaN, create an electron well (i.e., a sheet of electrons) at the interface between the two dissimilar materials resulting from the piezoelectric effect and spontaneous polarization effect therebetween.
Data Source
AI summary
A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.