SLCFET Series Stack Switching for Low-Loss High-Power RF Signals

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Solution Overview

Problem

SLCFET switch systems face limitations in handling high power and high frequency RF signals due to power requirements, losses, and non-linearities, particularly in switching device designs.

Innovation Solution

A super-lattice castellated field effect transistor (SLCFET) system is implemented with a series stack configuration, including gate resistors and balancing resistors to equalize drain-gate and gate-source voltages, providing a propagation path for RF signals with minimal losses and non-linearities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If SLCFETs are used to switch high power and high frequency RF signals, then RF signal switching capability is improved, but power requirements and losses increase

Engineering Contradiction:

ImproveRF signal power handling capabilityVSAvoidpower losses

Core Design Contradiction:

PowerVSLoss of energy

Solution Approach 1:

The patent divides the RF signal path into multiple parallel SLCFET switches rather than using a single device. Each SLCFET handles a portion of the total RF power, distributing the power handling burden and reducing losses in individual devices while maintaining overall high power capability.

Inventive Principle:

Principle #1Segmentation

2Speed

If SLCFETs are used to switch high frequency RF signals, then RF signal switching capability is improved, but non-linearities increase

Engineering Contradiction:

ImproveRF signal frequencyVSAvoidsignal linearity

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent combines multiple SLCFET switches in parallel to achieve the desired RF frequency performance. By merging the capabilities of multiple devices, the system maintains high frequency switching capability while the combined linear response of multiple devices reduces overall non-linearities compared to a single device operating at equivalent power levels.

Inventive Principle:

Principle #5Merging (Combining)

3Stress or pressure

If multiple SLCFETs are arranged in series stack, then voltage distribution is improved, but device complexity increases

Engineering Contradiction:

Improvevoltage distributionVSAvoidswitching device structure

Core Design Contradiction:

Stress or pressureVSDevice complexity

Solution Approach 1:

The patent uses balancing resistors connected to each SLCFET gate to equalize the voltage distribution across devices in a series stack. This creates equipotential conditions at the gate terminals, ensuring uniform voltage stress distribution across all SLCFETs in the series configuration, which improves reliability and prevents premature failure of individual devices.

Inventive Principle:

Principle #12Equipotentiality

Data Source

PatentUS20250105861A1Super-lattice castellated field effect transistor (slcfet) switch system

Publication Date: 2025.03.27 NORTHROP GRUMMAN SYSTEMS CORP

AI summary

One example includes a super-lattice castellated field effect transistor (SLCFET) system. The system includes a plurality of SLCFETs arranged in a series stack between a first port and a second port to provide a propagation path of a radio frequency (RF) signal between the first port and the second port in response to activation of the SLCFETs. The system also includes a plurality of gate resistors interconnecting gate terminals associated with each of the respective SLCFETs and an activation port to which an activation signal is provided to concurrently activate the SLCFETs. The system further includes a plurality of balancing resistors coupled to the gate terminals associated with each of the respective SLCFETs, the balancing resistors being configured to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the SLCFETs when activated.