Sleep FET Lifetime Extension via Selective Power Gating
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Solution Overview
Problem
Sleep FETs in power-gating arrays deteriorate over time due to bias temperature invariance (BTI) and time-dependent dielectric breakdown (TDDB), leading to increased voltage drop and potential failure, which can disrupt the ability to support maximum operating voltage of logic blocks.
Innovation Solution
Implementing a method that adjusts the operating voltage and selectively enables a subset of switching elements in power-gating arrays, reducing the usage of sleep FETs and distributing their activation evenly across all available elements to minimize deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If many sleep FETs are arranged in parallel to minimize resistance and support maximum operating voltage, then the voltage drop across the array is reduced, but the likelihood that a given FET will deteriorate and fail is increased
Solution Approach 1:
The patent implements dynamic selection of sleep FET subsets based on operational conditions. The system toggles between different subsets of sleep FETs depending on whether the logic block is operational or not, and selects from multiple available subsets to distribute usage. This dynamic approach prevents any single FET from being continuously activated, thereby extending individual FET lifetime while maintaining the required voltage support capability through the parallel array.
Solution Approach 2:
The patent changes the operational parameters of the sleep FET array by selectively enabling different subsets of FETs based on the operational state of the logic block. When the logic block is operational, a first subset of sleep FETs is enabled; when not operational, a second subset is enabled. This parameter change in subset selection distributes the stress and activation cycles across different FETs, extending their individual lifetimes while maintaining the overall reliability of the power-gating array.
2Loss of energy
If sleep FETs are continuously activated to prevent leakage when logic block is not operational, then power gating effectiveness is maintained, but FET deterioration due to BTI and TDDB is exacerbated
Solution Approach 1:
The patent divides the sleep FET array into multiple subsets and selectively activates different subsets based on operational requirements. Instead of continuously activating all sleep FETs or a single fixed subset, the system segments the FETs and rotates through different subsets, thereby reducing the cumulative stress on any individual FET while maintaining effective leakage prevention through the parallel configuration.
Solution Approach 2:
The patent implements periodic toggling between different subsets of sleep FETs. When the logic block transitions between operational and non-operational states, the system periodically switches between first and second subsets of sleep FETs. This periodic action distributes the activation cycles across different FETs over time, reducing individual FET deterioration from BTI and TDDB while maintaining continuous leakage prevention capability.
Data Source
AI summary
A power-gating array configured to power gate a logic block includes multiple zones of sleep field-effect transistors (FETs). A zone controller coupled to the power-gating array selectively enables a certain number of zones within the array depending on the voltage drawn by the logic block. When the logic block draws a lower voltage, the zone controller enables a lower number of zones. When the logic block draws a higher voltage, the zone controller enables a greater number of zones. One advantage of the disclosed technique is that sleep FET usage is reduced, thereby countering the effects of FET deterioration due to BTI and TDDB. Accordingly, the lifetime of sleep FETs configured to perform power gating for logic blocks may be extended.