Sleep-Enabled Logic Circuits for Leakage Reduction Without Timing Loss
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Solution Overview
Problem
Existing methods for reducing sleep state leakage current in electronic circuits, such as using additional AND gates or modifying logic gates, either increase circuit size, degrade timing, or require special libraries, and are inefficient in power conservation.
Innovation Solution
Implementing sleep enabled combinational logic, which includes replacing conventional output drivers with logic gates like NAND, NOR, or multiplexers that can switch between sleep and active states, allowing nodes to be preserved without adding extra gates, thus minimizing size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If additional AND gates are inserted at predefined nodes to force nodes to predetermined logic values during sleep state, then leakage current is reduced, but circuit size increases and timing degrades
Solution Approach 1:
The patent applies multi-functionality by making existing logic gates (AND, OR, NAND, NOR) perform both their original logic function and an additional function of forcing output to predetermined values during sleep state. This is achieved by modifying the gates to include sleep control inputs that enable them to output forced values (logic 0 or logic 1) when in sleep state, thereby eliminating the need for separate forcing gates and reducing overall circuit size.
Solution Approach 2:
The patent merges the function of sleep state forcing gates with the existing logic gates in the circuit. Instead of adding separate AND gates to force nodes to predetermined values, the forcing capability is integrated into the logic gates themselves by adding sleep control inputs. This consolidation reduces the number of components and simplifies the circuit structure while maintaining the leakage current reduction benefit.
2Loss of energy
If additional AND gates are inserted at predefined nodes to force nodes to predetermined logic values during sleep state, then leakage current is reduced, but timing degrades
Solution Approach 1:
The patent applies multi-functionality by making existing logic gates (AND, OR, NAND, NOR) perform both their original logic function and an additional function of forcing output to predetermined values during sleep state. This is achieved by modifying the gates to include sleep control inputs that enable them to output forced values (logic 0 or logic 1) when in sleep state, thereby eliminating the need for separate forcing gates and reducing overall circuit size.
Solution Approach 2:
The patent merges the function of sleep state forcing gates with the existing logic gates in the circuit. Instead of adding separate AND gates to force nodes to predetermined values, the forcing capability is integrated into the logic gates themselves by adding sleep control inputs. This consolidation reduces the number of components and simplifies the circuit structure while maintaining the leakage current reduction benefit.
3Loss of energy
If conventional cell libraries are not used and logic gates are modified to add transistors, then leakage current is reduced, but area increases and manufacturing complexity increases
Solution Approach 1:
The patent applies multi-functionality by making existing logic gates (AND, OR, NAND, NOR) perform both their original logic function and an additional function of forcing output to predetermined values during sleep state. This is achieved by modifying the gates to include sleep control inputs that enable them to output forced values (logic 0 or logic 1) when in sleep state, thereby eliminating the need for separate forcing gates and reducing overall circuit size.
4Loss of energy
If scan chain is used to scan in predefined output vector into latches to force outputs to specific values, then leakage current is reduced, but time and power are consumed during scanning
Solution Approach 1:
The patent applies preliminary action by pre-configuring the logic gates with sleep control inputs that enable them to automatically output predetermined values when entering sleep state. This eliminates the need for time-consuming scan operations to force nodes to specific values, as the forcing capability is already built into the gate structure and activates automatically based on the sleep state signal.
Data Source
AI summary
A circuit for reducing sleep state current leakage is described. The circuit includes a hardware unit selected from at least one of a latch, a flip-flop, a comparator, a multiplexer, or an adder. The hardware unit includes a first node. The hardware unit further includes a sleep enabled combinational logic coupled to the first node, wherein a value of the first node is preserved during a sleep state.