Sleep-Mode Voltage Regulator With Sub-Regulator Switching
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Solution Overview
Problem
Existing voltage regulators continue to consume current even in sleep mode due to the operation of the reference voltage circuit and operational amplifier, which is not thoroughly reduced.
Innovation Solution
A voltage regulator design that includes a reference voltage circuit and amplifier circuit that cease operation in sleep mode, along with a sub-regulator circuit that generates a lower power voltage for the output terminal, and utilizes a switch circuit to control the power-down of these components, reducing overall current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the reference voltage circuit and operational amplifier continue to operate in sleep mode, then voltage regulation stability is maintained, but current consumption is not reduced
Solution Approach 1:
The voltage regulator is segmented into two operational modes with different circuit configurations: normal mode using the reference voltage circuit and operational amplifier, and sleep mode using the sub-regulator circuit. This segmentation allows each circuit to be optimized for its specific operating condition, enabling complete power-down of high-consumption components in sleep mode while maintaining voltage regulation functionality.
Solution Approach 2:
The system dynamically switches between the main regulator circuit and the sub-regulator circuit based on operational mode. A mode switch control circuit transitions the regulator from normal operation to sleep mode by activating the sub-regulator circuit and disabling the reference voltage circuit and operational amplifier, thereby adapting the system's power consumption characteristics to match the current operational requirements.
2Loss of energy
If the reference voltage circuit and operational amplifier are powered down in sleep mode, then current consumption is reduced, but voltage regulation capability is lost
Solution Approach 1:
The sub-regulator circuit acts as an intermediary solution for sleep mode operation. It provides a simplified voltage regulation mechanism that operates independently of the main reference voltage circuit and operational amplifier, enabling the system to maintain basic voltage regulation capability while consuming minimal power during sleep mode.
Solution Approach 2:
The system changes its operational parameters by switching between full regulation mode (normal operation) and reduced regulation mode (sleep mode). In sleep mode, the sub-regulator circuit operates with reduced functionality and lower power consumption, appropriately matching the reduced performance requirements of devices in sleep state.
3Loss of energy
If a sub-regulator circuit is added to generate low power voltage, then sleep mode current consumption is reduced, but device complexity increases
Solution Approach 1:
The sub-regulator circuit is merged with the existing voltage regulator architecture, sharing common components such as the output capacitor and load connection. This integration allows the sleep mode circuit to be added without proportionally increasing overall system complexity, as it leverages existing structural elements rather than introducing completely separate systems.
Data Source
AI summary
Consumption current is reduced for a voltage regulator in sleep mode. In normal operation mode, a sub-regulator circuit is ceased from operating according to a power-down signal, which allows an operation amplifier to compare between a reference voltage outputted from a reference voltage circuit and a monitor voltage generated by a voltage-dividing circuit. Based on a detection voltage as a comparison result, a PMOS is controlled to regulate an internal power voltage such that the monitor voltage becomes equal to the reference voltage. In sleep mode, the reference voltage circuit and operational amplifier is ceased from operating, to start up the sub-regulator circuit. A slight current, restricted by a resistance, flows through a PMOS of the sub-regulator circuit. The same magnitude of current is supplied from the PMOS constituting a current mirror to a PMOS, etc. of a threshold-voltage output circuit. The threshold voltage, at a node between the PMOS constituting the current mirror and the PMOS of the threshold-voltage output circuit, is power-amplified by a voltage follower and outputted through an output terminal.