Programmable Sleep Transistor Array for Active-Mode Leakage Control
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Solution Overview
Problem
The increasing leakage power consumption in smaller transistors leads to the discard of both slow and fast dies, as existing methods fail to effectively manage leakage in active modes without degrading circuit performance.
Innovation Solution
A programmable sleep transistor array is used, where a sub-combination of sleep transistors can be turned on during active modes based on leakage characteristics, utilizing PMOS or NMOS transistors to provide a virtual supply and reduce leakage, allowing for the retention and use of previously discarded 'leaky' dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sleep transistors are turned off during active mode to maintain circuit performance, then circuit performance is maintained, but leakage power consumption increases
Solution Approach 1:
The sleep transistor array is divided into multiple individually controllable sleep transistors (e.g., 64 transistors in a 8x8 array). Each sleep transistor can be independently controlled through programmable logic, allowing selective activation of only those transistors needed to maintain circuit performance while keeping others off to reduce leakage. This segmentation enables fine-grained control over the trade-off between performance and leakage reduction.
Solution Approach 2:
The system dynamically adjusts the state of sleep transistors based on real-time leakage measurements and circuit performance requirements. During active mode, the programmable logic monitors leakage characteristics and selectively turns on or off individual sleep transistors, creating a dynamic configuration that adapts to varying leakage conditions while maintaining acceptable performance levels.
2Loss of energy
If a large number of sleep transistors are used to reduce leakage, then leakage reduction is improved, but device complexity increases
Solution Approach 1:
The programmable logic unit serves multiple functions: it controls the sleep transistor array, measures leakage characteristics, determines optimal transistor configurations, and manages the virtual supply voltage. This multi-functional approach consolidates what would otherwise require separate dedicated circuits, reducing overall device complexity while enabling sophisticated leakage management with a large transistor array.
Solution Approach 2:
The system performs self-characterization by automatically measuring its own leakage properties and using this information to configure the sleep transistor array optimally. The programmable logic autonomously determines which transistors to activate based on measured characteristics, eliminating the need for external configuration or complex hardwired control logic.
3Loss of energy
If fast but leaky dies are discarded to maintain low leakage, then leakage is controlled, but die utilization and productivity decrease
Solution Approach 1:
The system changes the operational parameters of the sleep transistor array based on measured leakage characteristics. By adjusting which transistors are active and configuring the virtual supply voltage appropriately, the system adapts to the specific leakage properties of each die, enabling fast but leaky dies to be utilized effectively rather than discarded.
Solution Approach 2:
The system implements a feedback loop where leakage characteristics are measured, processed by programmable logic to determine optimal configuration, and then used to control the sleep transistor array. This closed-loop feedback enables the system to compensate for high leakage in previously discarded dies, transforming them into usable products that meet performance and power requirements.
Data Source
AI summary
In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.