Sleeping Waking Address Translation for Page Table Walks
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Solution Overview
Problem
Current computing systems face performance issues when handling multiple page sizes due to stalling of new translation requests during address collisions, which hinders the advantages of multiple hardware table walk engines and slows down the system.
Innovation Solution
Implementing a sleep and wake-up interface and supporting hardware logic between a translation requestor and multiple translation table walk engines to allow overlap of simultaneous table walks, using active table walk engines' state to determine the number of VA bits to compare and temporarily putting new requests to sleep until they can proceed without address collisions, then waking them up to process in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If new translation requests are stalled during address collisions to ensure correct translation, then translation accuracy is maintained, but system throughput and productivity deteriorate
Solution Approach 1:
The system dynamically changes the state of translation requests from active to sleeping and back to active based on collision detection and completion status. The translation requestor module can put requests to sleep when collisions are detected and wake them up when the conflicting translation walk completes, allowing the system to adapt its behavior to current workload conditions while maintaining both accuracy and throughput
Solution Approach 2:
The system performs preliminary collision detection by comparing the virtual address of incoming translation requests with addresses of active translation walks before full processing begins. By detecting potential collisions early and putting requests to sleep proactively, the system prevents incorrect translations while minimizing the time requests spend stalled, thus maintaining both accuracy and productivity
2Productivity
If multiple table walk engines operate in parallel to increase throughput, then productivity improves, but address collision conflicts increase causing more stalls
Solution Approach 1:
The system implements feedback mechanisms where translation walk engines report their active addresses to the translation requestor module, which then uses this information to detect collisions and manage request states. This feedback loop allows parallel engines to coordinate their operations, reducing unnecessary stalls while maintaining high throughput
Solution Approach 2:
The translation requestor module acts as an intermediary between multiple parallel table walk engines and the translation cache. It receives translation requests, detects potential collisions by comparing addresses, manages the sleep/wake states of requests, and coordinates with active translation walks. This intermediary layer enables parallel operation of multiple engines while minimizing conflicts and stall time
Data Source
AI summary
A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.