Slew Dependent Pin Capacitance for VLSI Timing Abstraction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current static timing analysis (STA) methods for Very Large Scale Integrated (VLSI) circuits face inaccuracies due to the use of lumped pin capacitances, which can lead to significant errors in delay and slew calculations, especially in modern sub-65 nanometer designs with complex interconnect networks.
Innovation Solution
The method involves representing interconnect parasitics as slew dependent pin capacitances during timing abstraction, using charge matching and model order reduction techniques to accurately capture the parasitics of interconnect networks connected to macro primary inputs, thereby generating a more accurate abstract model that preserves the true RC or RLC network behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lumped pin capacitances are used to model interconnect parasitics, then the analysis complexity is reduced and computation is faster, but the accuracy of delay and slew calculations deteriorates significantly
Solution Approach 1:
The patent transforms the fixed lumped capacitance parameter into a slew-dependent variable parameter. The pin capacitance is modeled as a function of the slew rate at the driving gate output, allowing the capacitance value to adapt dynamically based on the actual signal transition characteristics. This resolves the contradiction by maintaining computational efficiency while significantly improving accuracy through parameter variability.
Solution Approach 2:
The invention introduces dynamics into the previously static capacitance model. Instead of using a constant lumped capacitance value, the pin capacitance becomes dynamic and adjusts according to the slew rate conditions. This dynamic modeling approach enables the system to maintain both speed and accuracy by adapting the capacitance representation to the actual operating conditions without requiring full complex interconnect analysis.
2Measurement precision
If higher order reduced models are used to capture interconnect behavior, then the accuracy of input-output behavior is improved, but the complexity of the analysis increases
Solution Approach 1:
The patent extracts the essential interconnect behavior characteristics and represents them through simplified slew-dependent capacitance functions rather than using complete higher-order reduced models. By taking out only the critical dynamic characteristics (slew-rate dependencies) and representing them in a compact functional form, the invention achieves good accuracy without the computational burden of full higher-order models.
Solution Approach 2:
The invention creates a simplified copy of the interconnect behavior through slew-dependent capacitance functions. Instead of using the full complex interconnect network or high-order reduced models, it creates an abstracted representation that captures the essential input-output behavior characteristics. This copied behavioral model maintains accuracy for timing analysis purposes while dramatically reducing analysis complexity.
3Reliability
If detailed interconnect parasitics are fully modeled, then the fidelity of timing analysis is improved, but the computation time and resource requirements increase
Solution Approach 1:
The patent performs preliminary characterization of the interconnect parasitics during the timing abstraction phase. The slew-dependent capacitance functions are pre-computed and stored based on detailed interconnect analysis performed beforehand. During actual timing analysis, these pre-characterized functions are used directly, avoiding the need to perform detailed interconnect modeling repeatedly. This preliminary action resolves the contradiction by maintaining high fidelity through accurate pre-computed models while reducing computation time during subsequent analyses.
Data Source
AI summary
A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.