Slew-Driven Clock Tree Synthesis for Low Voltage IC Power Reduction
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Solution Overview
Problem
Current clock tree synthesis methods struggle to effectively manage clock slew, particularly in low voltage integrated circuit designs, where increased interconnect resistance exacerbates slew constraints and power consumption, and traditional methods prioritize skew minimization over slew optimization.
Innovation Solution
The SLECTS methodology, which incorporates slew-driven clock tree synthesis, employs pair selection and cost metric definition considering physical distance for efficient sink clustering, slew and skew-aware merging point computation, and insertion delay-aware net splitting to simultaneously constrain skew and slew, thereby reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional skew-driven clock tree synthesis is used, then clock skew is minimized, but clock slew violations occur and power consumption increases
Solution Approach 1:
The patent changes the optimization parameter from skew-only to slew-driven optimization. The cost function is modified to prioritize slew constraint satisfaction over skew minimization, fundamentally changing the optimization objective to resolve the contradiction between skew performance and slew reliability
Solution Approach 2:
The patent applies local quality by making the merging process slew-aware at each step. The cost metric is locally adjusted to consider slew constraints for each candidate merging pair, ensuring that slew violations are prevented at critical nodes while maintaining overall tree optimization
2Loss of energy
If voltage is reduced to limit power density, then power consumption decreases, but clock slew constraints become more difficult to satisfy
Solution Approach 1:
The patent performs preliminary slew-aware optimization during the clock tree synthesis phase. By proactively considering slew constraints and optimizing the tree structure beforehand, the design can operate at lower voltages without subsequently violating slew constraints, enabling low-power operation
Solution Approach 2:
The patent introduces slew-aware cost metrics as an intermediary between voltage reduction and slew constraint satisfaction. This cost function acts as a mediator that guides the merging process to produce trees that can tolerate lower operating voltages while still meeting slew requirements
3Manufacturing precision
If interconnect resistance increases at new technology nodes, then manufacturing precision improves, but clock slew violations increase on long wires
Solution Approach 1:
The patent applies segmentation by carefully controlling the merging process to create a hierarchical tree structure. This segmentation approach breaks down long interconnects into manageable segments with appropriate buffering, reducing the impact of increased interconnect resistance at scaled technology nodes
4Measurement precision
If clock tree synthesis prioritizes skew minimization, then skew is reduced, but power dissipation increases
Solution Approach 1:
The patent inverts the traditional optimization priority by making slew constraint satisfaction the primary objective rather than skew minimization. This inversion leads to different merging decisions that reduce power dissipation while maintaining acceptable skew performance
Data Source
AI summary
A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and skew-aware merging point computation for routing; and slew and insertion slew-aware net splitting.